Printable semiconductor structures and related methods of making and assembling

• US 7,799,699 B2
• Filed: 06/01/2006
• Issued: 09/21/2010
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Board of Trustees of The University of Illinois
• Original Assignee: Board of Trustees of The University of Illinois
• Inventors: Lee, Keon Jae, Nuzzo, Ralph G., Menard, Etienne, Ko, Heung Cho, Mack, Shawn, Zhu, Zhengtao, Sun, Yugang, Khang, Dahl-Young, Meitl, Matthew, Rogers, John A.
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US11/421,654
• Publication Number:
  US 20070032089A1
• Time in Patent Office: 1,573 Days
• Field of Search: 438/758, 216/2, 156/384, 101/353
• US Class Current: 438/758
• CPC Class Codes: B81C 2201/0185 Printing, e.g. microcontact printing
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02628 using solutions
• CPC Class Codes: H01L 21/30 Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 manufacture of electrodes thereon H01L21/28
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/66265 Thin film bipolar transistors H01L29/66242 takes precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/72 Transistor-type devices, i.e. able to continuously respond to applied control signals
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 31/0392 : including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate textured substrates H01L31/02366
• CPC Class Codes: H01L 31/03925 : including AIIBVI compound materials, e.g. CdTe, CdS
• CPC Class Codes: H01L 31/03926 : comprising a flexible substrate
• CPC Class Codes: H01L 31/18 : Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H01L 31/1804 : comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/547 : Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.

Claims

1. A method for fabricating a printable semiconductor element, said method comprising the steps of:

providing a silicon wafer having a (111) orientation and having an external surface;

generating a plurality of recessed features on said external surface of said silicon wafer, wherein each of said recessed features comprises a bottom surface and side surfaces of exposed silicon wafer;

masking at least a portion of said side surfaces of said recessed features; and

etching between said recessed features, wherein etching occurs along <

110>

directions of said silicon wafer, thereby fabricating said printable semiconductor element.

2. The method of claim 1 wherein said side surfaces of said recessed features are completely masked.

3. The method of claim 1 wherein said side surfaces of said recessed features are partially masked.

4. The method of claim 1 wherein etching proceeds at a faster rate along said <

110>

directions of said silicon wafer than <

111>

directions of said silicon wafer.

5. The method of claim 1 wherein etching does not substantially proceed along the <

111>

directions of said silicon wafer.

6. The method of claim 1 wherein said step of etching between said recessed features comprises anisotropic etching of said silicon wafer.

7. The method of claim 1 wherein said step of etching between said recessed features proceeds between adjacent recessed features along the <

110>

directions of said silicon wafer, thereby at least partially undercutting said printable semiconductor element positioned between said adjacent recessed features.

8. The method of claim 1 wherein said step of etching between said recessed features comprises wet chemical etching using an anisotropic etchant.

9. The method of claim 1 wherein said recessed features comprise first and second channels separated from each other, wherein said step of etching between said recessed features proceeds from said first channel to said second channel along the <

110>

directions of said silicon wafer, thereby undercutting at least a portion of said printable semiconductor element between said first and second channels.

10. The method of claim 1 wherein said recessed features comprise an array of channels that are longitudinally oriented in a substantially parallel configuration, said method comprising a method of generating a plurality of printable semiconductor elements.

11. The method of claim 1 further comprising the step of growing a thermal oxide layer on said external surface of said silicon wafer after said step of generating said plurality of recessed features on said external surface.

12. The method of claim 1 further comprising the step of releasing said printable semiconductor element from said silicon wafer.

13. The method of claim 1 wherein said method is carried out more than once using said silicon wafer having said (111) orientation.

14. The method of claim 1 wherein said silicon wafer is a bulk silicon wafer.

15. The method of claim 1 wherein said silicon wafer is an undoped silicon wafer or a doped silicon wafer.

16. The method of claim 1 wherein said step of generating said plurality of recessed features on said external surface of said silicon wafer is carried out using one or more methods selected from the group consisting of:

photolithographic processing, dry chemical etching, plasma etching, wet chemical etching, micromachining, electron beam writing, reactive ion etching, soft lithographic processing, laser micromachining, ablation, mechanical machining, mechanical abrasion or scratching, drilling, and ion beam milling.

17. The method of claim 1 wherein said step of masking at least a portion of said side surfaces of said recessed features is carried out by one or more methods selected from the group consisting of:

angled electron beam evaporation of a mask material, chemical vapor deposition, thermal oxidation, and solution deposition of mask materials.

18. The method of claim 1 wherein said side surfaces of said recessed features have spatially varying contour profiles.

19. The method of claim 7 wherein said step of etching between said recessed features does not completely release said printable semiconductor from said silicon wafer, wherein at least one end of said printable semiconductor element is integrally connected to said silicon wafer.

20. The method of claim 8 wherein said anisotropic etchant is a basic solution.

21. The method of claim 9 wherein said first channel and said second channel are longitudinally oriented in a substantially parallel configuration, wherein said step of etching between said recessed features generates an at least partially undercut printable semiconductor ribbon positioned between said first and second channels.

22. The method of claim 9, wherein said first channel and said second channel are longitudinally oriented in a substantially parallel configuration, wherein said step of etching between said recessed features generates an entirely undercut printable semiconductor ribbon positioned between said first and second channels.

23. The method of claim 21 wherein at least one end of said printable semiconductor ribbon is integrally connected to said silicon wafer.

24. The method of claim 23 wherein said first channel terminates at a first end and said second channel terminates at a second end, and wherein said printable semiconductor ribbon is integrally connected to said silicon wafer between said first end of said first channel and said second end of said second channel.

25. The method of claim 24 wherein said first channel terminates at a third end and said second channel terminates at a fourth end, and wherein said printable semiconductor ribbon is integrally connected to said silicon wafer between said third end of said first channel and said fourth end of said second channel.

26. The method of claim 12 wherein said step of releasing said printable semiconductor element from said silicon wafer is carried out by contacting said printable semiconductor element with a transfer device.

27. The method of claim 12 further comprising the step of refinishing said silicon wafer such that said external surface after release of said printable semiconductor element becomes flat, said method further comprising repeating said steps of (i) generating a plurality of recessed features on said external surface of said silicon wafer, (ii) masking at least a portion of said side surfaces of said recessed features, and (iii) etching between said recessed features, thereby generating additional printable semiconductor elements.

28. The method of claim 26 wherein said transfer device is an elastomeric stamp.

29. The method of claim 18 wherein said spatially varying contour profiles have a plurality of ridges or recessed features or have a scalloped shape.

30. The method of claim 29 wherein selected portions but not all of said side surfaces having said spatially varying contour profiles are masked, wherein said etching between said recessed features generates a multilayer array of printable semiconductor elements.

31. A method for fabricating a printable semiconductor element, said method comprising the steps of:

providing a silicon wafer having a (111) orientation and having an external surface;

generating a plurality of recessed features on said external surface of said silicon wafer, wherein each of said recessed features comprises a bottom surface and side surfaces of exposed silicon wafer, wherein said recessed features comprise first and second channels separated from each other;

masking at least a portion of said side surfaces of said first and second channels; and

etching between said first and second channels, wherein etching occurs along <

110>

directions of said silicon wafer and proceeds from said first channel to said second channel along the <

110>

directions of said silicon wafer, thereby undercutting at least a portion of said printable semiconductor element between said first and second channels, thereby fabricating said printable semiconductor element.

32. The method of claim 31 wherein said first channel and said second channel are longitudinally oriented in a substantially parallel configuration, wherein said step of etching between said first and second channels generates an at least partially undercut printable semiconductor ribbon positioned between said first and second channels.

33. The method of claim 32 wherein said first channel terminates at a first end and said second channel terminates at a second end, and wherein said printable semiconductor ribbon is integrally connected to said silicon wafer between said first end of said first channel and said second end of said second channel.

34. The method of claim 33 wherein said first channel terminates at a third end and said second channel terminates at a fourth end, and wherein said printable semiconductor ribbon is integrally connected to said silicon wafer between said third end of said first channel and said fourth end of said second channel.

35. A method for fabricating a printable semiconductor element, said method comprising the steps of:

providing a silicon wafer having a (111) orientation and having an external surface;

generating a plurality of recessed features on said external surface of said silicon wafer, wherein each of said recessed features comprises a bottom surface and side surfaces of exposed silicon wafer;

masking at least a portion of said side surfaces of said recessed features;

etching between said recessed features, wherein etching occurs along <

110>

directions of said silicon wafer, thereby fabricating said printable semiconductor element; and

releasing said printable semiconductor element from said silicon wafer by contacting said printable semiconductor element with an elastomeric stamp.

36. The method of claim 35 wherein said step of releasing said printable semiconductor element comprises separating said printable semiconductor element from said silicon wafer.

37. The method of claim 35 wherein said step of releasing said printable semiconductor element comprises conformally contacting an external surface of said printable semiconductor element with said elastomeric stamp.

38. The method of claim 35 wherein contacting said printable semiconductor element with said elastomeric stamp binds said printable semiconductor element to said elastomeric stamp.

39. The method of claim 35 wherein said step of releasing said printable semiconductor element transfers said printable semiconductor element to said elastomeric stamp.

40. The method of claim 35 further comprising refinishing the external surface of the silicon wafer after release of said printable semiconductor element such that the external surface of said silicon wafer becomes flat.

41. The method of claim 40, wherein said method further comprises repeating said steps of (i) generating a plurality of recessed features on said external surface of said silicon wafer, (ii) masking at least a portion of said side surfaces of said recessed features, and (iii) etching between said recessed features, thereby generating additional printable semiconductor elements.