Semiconductor device and method of forming the same

• US 7,800,158 B2
• Filed: 11/16/2006
• Issued: 09/21/2010
• Est. Priority Date: 11/17/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-Hun, Kang, Sung-Taeg, Han, Jeong-Uk, Jeon, Hee-Seog
• Primary Examiner(s): Weiss; Howard
• Assistant Examiner(s): RAO, SHRINIVAS H
• Application Number:
  US11/600,499
• Publication Number:
  US 20070126048A1
• Time in Patent Office: 1,405 Days
• Field of Search: 257/316, 257/900, 257/416
• US Class Current: 257/316
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

Claims

1. A semiconductor device comprising:

a non-volatile memory device formed on a substrate, the non-volatile memory device comprising a stacked gate structure having a floating gate, a control gate, and an insulation layer formed between the floating gate and the control gate;

a first selection device formed on the substrate at one side of the non-volatile memory device;

a floating junction formed in the substrate between the non-volatile memory device and the first selection device; and

a spacer formed on one sidewall of the stacked gate structure in the non-volatile memory device adjacent to a gate of the first selection device, the spacer completely covering the floating junction between the non-volatile memory device and the first selection device and extending toward a sidewall of the gate in the first selection device;

wherein the gate of the first selection device is formed of a single-layered conductive layer.

2. The semiconductor device of claim 1, wherein the floating gate of the non-volatile memory device and the gate of the first selection device are formed of the same material.

3. The semiconductor device of claim 1, further comprising a drain formed in the substrate outside the non-volatile memory device opposite to the floating junction, and a source formed in the substrate outside the first selection device opposite to the floating junction.

4. The semiconductor device of claim 1, wherein the insulation layer of the non-volatile memory device comprises silicon oxide layer/silicon nitride layer/silicon oxide layer (ONO).

5. The semiconductor device of claim 1, further comprising a second spacer formed on the other sidewall in the gate of the first selection device opposite to the spacer, the spacer formed on the one sidewall of the non-volatile memory device having a height higher than that of the second spacer formed on the other sidewall.

6. The semiconductor device of claim 1, wherein a drain of the non-volatile memory device is connected to a bit line and a source of the selection device is electrically connected to a common source line.

7. The semiconductor device of claim 6, wherein the gate of the first selection device and the floating gate of the stacked gate structure of the non-volatile memory device are formed of the same material and have a substantially identical height.

8. The semiconductor device of claim 1, further comprising an oxide layer between the spacer and the stacked gate structure of the non-volatile memory device.

9. The semiconductor device of claim 1, further comprising:

a second selection device formed on the substrate at the other side of the non-volatile memory device, and including a gate formed of a single-layered conductive layer; and

a second floating junction formed on the substrate between the gate of the second selection device and the non-volatile memory device.

10. The semiconductor device of claim 9, further comprising a first spacer formed on sidewalls of the stacked gate structure in the non-volatile memory device, covering the first and second floating junction;

and

a second spacer formed on a sidewall of the first and second selection devices having a height lower than that of the first spacer.

11. A semiconductor device comprising:

a non-volatile memory device including a gate insulation layer, a floating gate, an inter-layer insulation layer, and a control gate on a substrate;

a selection device formed at one side of the non-volatile memory device;

a floating junction shared between the non-volatile memory device and the selection device;

a first sidewall spacer formed on a sidewall of the non-volatile memory device adjacent to the selection device, the first sidewall spacer completely covering the floating junction between the non-volatile memory device and the selection device and extending toward a sidewall of the selection device; and

a second sidewall spacer formed on the other sidewall of the selection device, and having a height lower than that of the first sidewall spacer.

12. The semiconductor device of claim 11, wherein the selection device comprises a selection gate formed of a material and having a height identical to that of the floating gate of the non-volatile memory device.

13. The semiconductor device of claim 11, wherein the non-volatile memory device and the selection device further comprise a source and a drain.

14. The semiconductor device of claim 12, wherein a drain of the non-volatile memory device is connected to the bit line and a source of the selection device is connected to a common source line.

15. The semiconductor device of claim 13, further comprising another selection device connected electrically to the common source line, and another non-volatile memory device with a drain connected electrically to the bit line.

16. The semiconductor device of claim 14, further comprising another selection device formed on the other side of the non-volatile memory device.