Non-volatile semiconductor storage device
First Claim
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1. A non-volatile semiconductor storage device comprising:
- a substrate;
a control circuit layer provided on the substrate;
a support layer provided on the control circuit layer; and
a memory cell array layer provided on the support layer,the memory cell array layer comprising;
a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and
a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers,the first lamination part comprising;
a third insulation layer provided in contact with the respective sidewalls of the first insulation layers and the first conductive layers;
a charge accumulation layer provided in contact with the third insulation layer and accumulating charges;
a fourth insulation layer provided in contact with the charge accumulation layer; and
a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction,the second lamination part comprising;
a fifth insulation layer provided in contact with the respective sidewalls of the second insulation layers and the second conductive layer; and
a second semiconductor layer provided in contact with the fifth insulation layer and the first semiconductor layer and formed to extend to the lamination direction, andthe control circuit layer comprising at least any one of;
a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.
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Abstract
A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.
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Citations
11 Claims
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1. A non-volatile semiconductor storage device comprising:
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a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer, the memory cell array layer comprising; a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers, the first lamination part comprising; a third insulation layer provided in contact with the respective sidewalls of the first insulation layers and the first conductive layers; a charge accumulation layer provided in contact with the third insulation layer and accumulating charges; a fourth insulation layer provided in contact with the charge accumulation layer; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction, the second lamination part comprising; a fifth insulation layer provided in contact with the respective sidewalls of the second insulation layers and the second conductive layer; and a second semiconductor layer provided in contact with the fifth insulation layer and the first semiconductor layer and formed to extend to the lamination direction, and the control circuit layer comprising at least any one of; a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification
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Current AssigneeKioxia Corporation
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsIzumi, Tatsuo, Kamigaichi, Takeshi
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Primary Examiner(s)Purvis; Sue
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Assistant Examiner(s)Ahmed; Selim
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Application NumberUS12/245,199Publication NumberTime in Patent Office718 DaysField of Search365/185.18, 365/185.27, 365/185.28, 257/315, 257/324, 257/326, 257/331, 257/E29.309, 257/E21.41, 257/E21.679, 257/E27.081, 257/E27.103US Class Current257/324CPC Class CodesH10B 43/20 characterised by three-dime...H10B 43/27 the channels comprising ver...H10B 43/30 characterised by the memory...H10B 69/00 Erasable-and-programmable R...
