Electronic circuit for controlling a power field effect transistor

• US 7,800,176 B2
• Filed: 10/27/2008
• Issued: 09/21/2010
• Est. Priority Date: 10/27/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Werner, Wolfgang
• Primary Examiner(s): Soward; Ida M
• Application Number:
  US12/258,988
• Publication Number:
  US 20100102871A1
• Time in Patent Office: 694 Days
• Field of Search: 257328-330, 257/341, 257/367, 257/401, 257/409, 257/E29.009, 257/E29.017
• US Class Current: 257/341
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12035 : Zener diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03K 17/687 : the devices being field-effect transistors

Abstract

An electronic circuit and a method for controlling a power field effect transistor. The electronic circuit includes a power field effect transistor having a semiconductor body, which has a drain zone, a drift zone, a source zone and a bulk zone. The power field effect transistor further includes a gate and a field plate. The field plate is placed adjacent to the drift zone and is isolated from the drift zone. A switch circuitry is provided for electrically connecting the field plate depending on the drain-source voltage such that the field plate is electrically connected to the drain zone, if |UDS|>UT, where UT is a predetermined voltage, and if |UDS|>UT, the field plate is connected to an electrode having an electrode-source voltage UES.

Claims

1. An electronic circuit, comprising:

a power field effect transistor (FET) including a semiconductor body, the semiconductor body including a drain zone, a drift zone, a source zone and a bulk zone, the power FET further including a gate and a field plate, the field plate being placed adjacent to the drift zone and being insulated from the drift zone;

a switch circuitry for electrically connecting the field plate dependent on the drain-source voltage UDS and a predetermined voltage UT, such that

the field plate is electrically connected to the drain zone if |UDS|<

UT, and

if |UDS|>

UT, the field plate is electrically connected to an electrode having an electrode-source voltage UES between the electrode and the source with |UES|<

|UDS|.

2. The electronic circuit of claim 1, wherein the field plate is connected to the source zone, if |UDS|>

UT.

3. The electronic circuit of claim 1, wherein the field plate is connected to the gate, if |UDS|>

UT.

4. The electronic circuit of claim 1, wherein the switch circuitry includes a series connection of at least one diode and at least one resistor coupled between the drain zone and the source zone, one of the electrodes anode and cathode of the diode being coupled to the source zone and the other of the electrodes anode and cathode of the diode being coupled to the field plate.

5. The electronic circuit of claim 1, wherein the switch circuitry is integrated on the same integrated circuit as the power FET.

6. The electronic circuit of claim 1, wherein the field plate-source voltage UFPS is constant for the |UDS|>

UT.

7. The electronic circuit of claim 1, wherein the predetermined voltage UT is smaller than the drain-source voltage during an avalanche break-through of the power FET.

8. The electronic circuit of claim 1, wherein the switch circuitry includes a series connection of at least a diode-connected transistor and at least one resistor between the drain zone and the source zone, the diode-connected transistor being coupled between the source zone and the field plate.

9. The electronic circuit of claim 1, wherein the switch circuitry includes a series connection of at least one transistor and at least one resistor between the drain zone and the source zone, the transistor being arranged to couple the source zone or the drain zone with the field plate dependent on the voltage at a control terminal of the transistor.

10. The electronic circuit of claim 1, wherein the field plate includes semiconductor material having a doping concentration >

2*10¹⁶*cm<sup>−

3</sup>.

11. The electronic circuit of claim 1, wherein the switch circuitry comprises:

a first switch connected between a drain electrode and the field plate; and

a second switch connected between the field plate and a source electrode.

12. The electronic circuit of claim 1, wherein the switch circuitry comprises:

a first switch connected between a drain electrode and the field plate; and

a second switch connected between the field plate and the gate.

13. The electronic circuit of claim 1, wherein the switch circuitry comprises:

a diode having an anode connected to a source electrode and a cathode connected to the field plate; and

a resistor connected between the field plate and a drain electrode.

14. The electronic circuit of claim 13, wherein the diode a zener diode.

15. The electronic circuit of claim 1, wherein the switch circuitry comprises:

a resistor connected between the drain zone and the field plate;

a transistor having a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is connected to the field plate and the source terminal connected to the source zone of the FET.

16. The electronic circuit of claim 15, wherein the transistor includes a plurality of transistors connected in series between the source zone of the FET and the field plate, wherein each of the plurality of transistors has its drain terminal connected to its gate terminal.

17. The electronic circuit of claim 1, wherein the switch circuitry comprises:

first and second resistors connected in series between a source electrode and a drain electrode such that a first terminal of the first resistor is connected to the source electrode, and a second terminal of the first resistor is connected to a first terminal of the second resistor, and a second terminal of the second resistor is connected to the drain electrode;

a third resistor and a transistor connected in series between the source electrode and the gain electrode such that a source terminal of the transistor is connected to the source electrode, a gate terminal of the transistor is connected to the second terminal of the first resistor and the first terminal of the second resistor, and a drain terminal is connected to the field plate.