Closed trench MOSFET with floating trench rings as termination

• US 7,800,185 B2
• Filed: 01/28/2007
• Issued: 09/21/2010
• Est. Priority Date: 01/28/2007
• Status: Active Grant

• Current Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Original Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Inventors: Hshieh, Fwu-Iuan
• Primary Examiner(s): Maldonado; Julio J
• Assistant Examiner(s): Kim; Su C
• Application Number:
  US11/699,256
• Publication Number:
  US 20080179662A1
• Time in Patent Office: 1,332 Days
• Field of Search: 257/401, 257/409, 257335-350, 257/E29.257, 257/E29.26, 257/E21.418, 257/E21.419, 438/140, 438/170, 438/FOR.230
• US Class Current: 257/401
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor power device includes a plurality of closed N-channel MOSFET cells surrounded by trenched gates constituting substantially a square or rectangular cell. The trenched gates are further extended to a gate contact area and having greater width as wider trenched gates for electrically contacting a gate pad wherein the semiconductor power device further includes a source region disposed only in regions near the trenched gates in the closed N-channel MOSFET cells and away from regions near the wider trenched gate whereby a device ruggedness is improved. The source region is further disposed at a distance away from a corner or an edge of the semiconductor power device and away from a termination area. The semiconductor device further includes multiple trenched rings disposed in a termination area opposite the active area and the trenched rings having a floating voltage. The closed N-channel MOSFET cells are further supported on a red phosphorous substrate.

Claims

1. A semiconductor power device comprising:

a plurality of power transistor cells disposed in an active area near a top surface of an epitaxial layer of first conductivity type grown on a semiconductor substrate of said first conductivity type wherein each of said transistor cells is surrounded by trenched gates;

multiple trenched floating rings disposed in a termination area surrounding said active area and each of said trenched floating rings filled with a doped polysilicon layer of said first conductivity type padded by a gate insulation layer in a trench having a floating voltage wherein said trenched floating rings further penetrating through a body region and extending into said epitaxial layer;

said body region of a second conductivity type formed in both said active cell area and said termination area disposed immediately adjacent to said trenched floating rings;

said trenched gates further extended to a gate contact area having a greater width than said trench gates in said active cell area as wider trenched gates for electrically contacting a gate pad; and

a source region of said first conductivity type disposed only in said active area but not in said termination area comprising said multiple trenched floating rings and no source regions disposed in said epitaxial layer regions adjacent to said wider trenched gate in said gate contact area.

2. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising N-channel MOSFET cells and said source region further comprising N+ doped source region disposed only in said active area but not in said termination area comprising said multiple trenched floating rings filled with an N+ doped polysilicon layer padded with said gate insulation layer and no N+ dopant regions disposed in said epitaxial layer adjacent to said wider trenched gate in said gate contact area.

3. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising P-channel MOSFET cells and said source region further comprising P+ doped source region disposed only in said active area but not in said termination area comprising said multiple trenched floating rings filled with a P+ doped polysilicon layer padded with said gate insulation layer and no P+ dopant regions disposed in said epitaxial layer adjacent to said wider trenched gate in said gate contact area.

4. The semiconductor power device of claim 1 further comprising:

an insulation layer overlying said semiconductor device and a plurality of source-body contact opened through said insulation layer and said source region and extending into said body region for filling with a source-body contact plug therein for electrically contacting said source region and said body region; and

a plurality of gate contact opened through said insulating layer and extending into said wider trenched gates wider than said trench gates in said active cell area for filling with a gate-contact metal plug therein for electrically contacting said wide trenched gate disposed in said epitaxial layer having no source regions adjacent to said wider trenched gate.

5. The semiconductor power device of claim 4 further comprising:

a patterned source metal layer and a patterned gate pad disposed on top of said insulating layer for electrically contacting said source-body contact plug and said gate-contact plugs respectively.

6. The semiconductor power device of claim 1 wherein:

said multiple trenched floating rings in said termination comprising at least three trenched rings.

7. The semiconductor power device of claim 1 wherein:

said multiple trenched floating rings in said termination having equal space between one another.

8. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising N-channel MOSFET cells disposed near the top surface of said epitaxial layer supported on a red phosphorous substrate.

9. The semiconductor power device of claim 1 further comprising

a drain electrode disposed on a bottom surface of a said semiconductor substrate supporting said semiconductor power device with said trenched gates and source region disposed near the top surface of said epitaxial layer.

10. A semiconductor power device comprising:

a plurality of N channel or P-channel MOSFET cells surrounded by trenched gates in an active area near a top surface of an epitaxial layer of first conductivity grown on a substrate of first conductivity type;

said trenched gates further extended to a gate contact area and having greater width as wider trenched gates than said trench gates in said active cell area for electrically contacting a gate pad;

at least three trenched floating rings disposed in a termination area surrounding said active cell area and said trenched floating rings filled with a doped polysilicon layer of said first conductivity type padded by a gate insulation layer in a trench having a floating voltage wherein said trenched floating rings penetrating through a body region and extending into said epitaxial layer;

said body region of a second conductivity type formed in both said active cell area and said termination area disposed immediately adjacent to said trenched floating rings;

a source region of said first conductivity type disposed only in said active area but not in said termination area having said multiple trenched floating rings and no source regions disposed in said epitaxial layer adjacent to said wider trenched gate in said gate contact area;

an insulation layer overlying said semiconductor device and a plurality of source-body contact trenches opened through said insulation layer and said source region and extending into said body region for filling with a source-body contact metal plug therein for electrically contacting said source region and said body region;

a patterned source metal layer disposed on top of said insulating layer for electrically contacting said source-body contact plug; and

a drain electrode disposed on a bottom surface of a semiconductor substrate supporting said semiconductor power device.

11. The semiconductor power device of claim 10 wherein:

said N-channel MOSFET cells are disposed near top surface of said epitaxial layer supported on a red phosphorous substrate.