Semiconductor structure with an electric field stop layer for improved edge termination capability

• US 7,800,196 B2
• Filed: 09/30/2008
• Issued: 09/21/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Inventors: McNutt, Ty R., Veliadis, John Victor D.
• Primary Examiner(s): Wilczewski; Mary
• Application Number:
  US12/285,138
• Publication Number:
  US 20100078755A1
• Time in Patent Office: 721 Days
• Field of Search: 257/77, 257/263, 257/496, 257/E29.023, 257/E29.262
• US Class Current: 257/496
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7325 having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8083 : Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/8613 : Mesa PN junction diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An exemplary edge termination structure maintains the breakdown voltage of the semiconductor device after it has been sawed off the wafer and packaged by creating an electric field stop layer at a periphery of the semiconductor device. The electric field stop layer has a dopant concentration higher than that of the layer in which an edge termination is implemented, such as a drift layer or a channel layer. The electric field stop layer may be created by selectively masking the peripheries of the device during the device processing, i.e., mesa etch, to protect and preserve the highly doped material at the peripheries of the device.

Claims

1. An edge termination structure for a semiconductor device, comprising:

a first n-type semiconductor layer having a first dopant concentration and situated on a top surface of a semiconductor substrate;

a second n-type semiconductor layer having a second dopant concentration that is higher than the first dopant concentration of the first n-type semiconductor layer, and situated on a top surface of the first n-type semiconductor layer, wherein the first n-type semiconductor layer is sandwiched between the semiconductor substrate and the second n-type semiconductor layer;

a mesa extending through the second n-type semiconductor layer and terminating into the first n-type semiconductor layer, wherein the edge termination structure is formed in the first n-type semiconductor layer surrounding a bottom of the mesa; and

an n-type electric field semiconductor stop layer formed at a periphery of the semiconductor device having a third dopant concentration higher than the first dopant concentration of the first n-type semiconductor layer and approximately the same as the second dopant concentration of the second n-type semiconductor layer, wherein a top surface of the n-type electric field semiconductor stop layer is at a same elevation as a top surface of the second n-type semiconductor layer.

2. The structure of claim 1, wherein the mesa is etched along a slope.

3. The structure of claim 1, wherein the mesa is etched vertically.

4. The structure of claim 1, wherein the mesa is etched using one or more of a resist pattern, a dielectric pattern, and a metal pattern.

5. The structure of claim 1, wherein the electric field stop layer is formed at the periphery of the semiconductor device after etching the mesa.

6. The structure of claim 1, wherein the semiconductor device is selected from the group consisting of a silicon carbide (SiC), a diamond, a Galium Arsenide (GaAs), a Galium Nitride (GaN), an Aluminum-Galium-Nitride/Galium-Nitride, and an Indium-Galium-Nitride/Galium-Nitride material based power device.

7. The structure of claim 1, wherein when the semiconductor device is sawed off a wafer and packaged, a second breakdown voltage of the semiconductor device is approximately the same as a first breakdown voltage of the semiconductor device when the semiconductor device is on the wafer.

8. The structure of claim 1, wherein the semiconductor device is a vertical semiconductor device that blocks voltage.

9. The structure of claim 8, wherein the vertical semiconductor device is one of a vertical-junction field-effect-transistor (VJFET), an ion-implanted static induction transistor (SIT), a diode, a metal-oxide-semiconductor field-effect-transistor (MOSFET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), and a rectifier.

10. An edge termination structure for a semiconductor device, comprising:

an n-type semiconductor substrate;

an n-type semiconductor drift layer situated on a top surface of the n-type semiconductor substrate;

an n-type semiconductor channel layer situated on a top surface of the n-type semiconductor drift layer, wherein the n-type semiconductor draft layer is sandwiched between the n-type semiconductor substrate and the n-type semiconductor channel layer;

an n-type semiconductor source layer situated on a top surface of the n-type semiconductor channel layer, wherein the n-type semiconductor channel layer is sandwiched between the n-type semiconductor drift layer and the n-type semiconductor source layer, and wherein a dopant concentration of the source layer is higher than a dopant concentration of the drift layer and a dopant concentration of the channel layer;

a mesa extending through the n-type semiconductor source layer, wherein the edge termination structure is formed in an area surrounding a bottom of the mesa; and

an n-type electric field semiconductor stop layer formed at a periphery of the semiconductor device having a dopant concentration approximately the same as the dopant concentration of the n-type semiconductor source layer, wherein a top surface of the n-type electric field semiconductor stop layer is at a same elevation as a top surface of the n-type semiconductor source layer.

11. The structure of claim 10, wherein the bottom of the mesa is in the n-type semiconductor drift layer.

12. The structure of claim 10, wherein the bottom of the mesa is in the n-type semiconductor channel layer.

13. The structure of claim 10, wherein the electric field stop layer is formed at the periphery of the semiconductor device after etching a mesa.

14. The structure of claim 10, wherein the semiconductor device is selected from the group consisting of a silicon carbide (SiC), a diamond, a Galium Arsenide (GaAs), a Galium Nitride (GaN), an Aluminum-Galium-Nitride/Galium-Nitride, and an Indium-Galium-Nitride/Galium-Nitride material based power device.

15. The structure of claim 10, wherein when the semiconductor device is sawed off a wafer and packaged, a second breakdown voltage of the semiconductor device is approximately the same as a first breakdown voltage of the semiconductor device when the semiconductor device is on the wafer.

16. The structure of claim 10, wherein the semiconductor device is a vertical semiconductor device that blocks voltage and is selected from a group consisting of a vertical-junction field-effect-transistor (VJFET), an ion-implanted static induction transistor (SIT), a diode, a metal-oxide-semiconductor field-effect-transistor (MOSFET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), and a rectifier.