Semiconductor circuit

• US 7,800,199 B2
• Filed: 02/29/2008
• Issued: 09/21/2010
• Est. Priority Date: 06/24/2003
• Status: Expired due to Fees

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun, Oh, ChoonSik
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US12/040,642
• Publication Number:
  US 20080191312A1
• Time in Patent Office: 935 Days
• Field of Search: 257/532, 257/E21.122, 257/E21.482, 257/E21.505, 257/E21.614, 438/458, 438/459, 438/479
• US Class Current: 257/532
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01038 Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01056 Barium [Ba]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A capacitor is connected to the electronic device so that the electronic device and capacitor operate as a dynamic random access memory device.

Claims

1. A semiconductor circuit, comprising:

a carrier substrate which carries an interconnect region;

a bonding layer which includes electrically conductive material;

a donor layer coupled to the interconnect region through the bonding layer, wherein the donor layer includes a polished surface which faces the bonding layer; and

an electronic device carried by the donor layer.

2. The circuit of claim 1, wherein the interconnect region includes a refractory metal.

3. The circuit of claim 1, wherein the electronic device is positioned away from the bonding layer.

4. The circuit of claim 1, wherein the electronic device is a horizontally oriented device or vertically oriented device.

5. The circuit of claim 1, further including a capacitor connected to the electronic device.

6. The circuit of claim 5, wherein the capacitor is formed after the bonding layer is formed.

7. The circuit of claim 1, wherein the electronic device operates as a static random access memory device.

8. The circuit of claim 1, wherein the electronic device operates as a non-volatile memory device.

9. The circuit of claim 1, wherein the donor layer includes a polished surface opposed to the polished surface which faces the bonding layer.

10. The circuit of claim 1, wherein the donor layer includes a polished surface proximate to the electronic device and opposed to the polished surface which faces the bonding layer.

34. The circuit of claim 1, wherein the bonding layer includes a metal.

35. The circuit of claim 1, wherein the donor layer includes semiconductor material.

36. The circuit of claim 1, wherein the donor layer includes crystalline semiconductor material.

37. The circuit of claim 1, wherein the donor layer includes single crystalline semiconductor material.

38. The circuit of claim 1, wherein the carrier substrate includes semiconductor material.

39. The circuit of claim 1, wherein the carrier substrate carries a transistor in communication with the interconnect region.

40. The circuit of claim 1, wherein the carrier substrate includes CMOS circuitry in communication with the interconnect region.

41. The circuit of claim 1, wherein the electronic device is a horizontally oriented device.

42. The circuit of claim 1, wherein the electronic device is a vertically oriented device.

43. The circuit of claim 1, wherein the polished surface is a semiconductor surface.

11. A semiconductor circuit, comprising:

an interconnect region;

a first bonding layer which includes electrically conductive material;

a donor layer bonded to the interconnect region through the first bonding layer, wherein the donor layer includes first and second opposed polished surfaces, the first polished surface facing the bonding layer; and

an electronic device positioned proximate to the second polished surface.

12. The circuit of claim 11, further including a second bonding layer which bonds the electronic device to the second polished surface.

13. The circuit of claim 11, further including a capacitor connected to the electronic device.

14. The circuit of claim 13, wherein the electronic device is a horizontally oriented electronic device.

15. The circuit of claim 11, further including an isolation region which extends through the second polished surface.

16. The circuit of claim 11, wherein the first bonding layer extends between the first polished surface and interconnect region.

17. The circuit of claim 12, wherein the electronic device is a horizontally oriented device.

18. The circuit of claim 14, wherein the electronic device is a vertically oriented device which includes a mesa structure.

19. The circuit of claim 18, wherein the mesa structure includes a stack of crystalline semiconductor material layers.

44. The circuit of claim 11, wherein the first bonding layer includes a metal.

45. The circuit of claim 12, wherein the second bonding layer includes electrically conductive material.

46. The circuit of claim 11, wherein the donor layer includes semiconductor material.

47. The circuit of claim 11, wherein the first polished surface is a polished semiconductor surface.

48. The circuit of claim 11, wherein the second polished surface is a polished semiconductor surface.

49. The circuit of claim 19, wherein the bonding layer includes a metal.

50. The circuit of claim 19, wherein the donor layer includes semiconductor material.

51. The circuit of claim 19, wherein the donor layer includes crystalline semiconductor material.

52. The circuit of claim 19, wherein the donor layer includes single crystalline semiconductor material.

53. The circuit of claim 19, wherein the carrier substrate includes semiconductor material.

54. The circuit of claim 19, wherein the carrier substrate carries a transistor in communication with the interconnect region.

55. The circuit of claim 19, wherein the carrier substrate includes CMOS circuitry in communication with the interconnect region.

56. The circuit of claim 19, wherein the electronic device is a horizontally oriented device.

57. The circuit of claim 19, wherein the electronic device is a vertically oriented device.

58. The circuit of claim 19, wherein the polished surface is a semiconductor surface.

20. A semiconductor circuit, comprising:

a carrier substrate which carries an interconnect region;

a first bonding layer which includes electrically conductive material;

a donor layer bonded to the interconnect region through the first bonding layer, wherein the donor layer includes a first polished surface which faces the first bonding layer; and

a first electronic device carried by the donor layer, wherein the first electronic device is formed proximate to a surface opposed to the first polished surface.

21. The circuit of claim 20, wherein the surface opposed to the first polished surface is a second polished surface.

22. The circuit of claim 20, further including a second electronic device positioned proximate to the carrier substrate, wherein the first and second electronic devices are in communication with each other through the interconnect region.

23. The circuit of claim 21, further including a capacitor operatively coupled to the electronic circuit, wherein the first and second polished surfaces extend between the capacitor and interconnect region.

24. The circuit of claim 20, wherein the donor layer has a graded doping concentration.

25. The circuit of claim 24, wherein the doping concentration of the donor layer is greater proximate to the first polished surface than the surface opposed to the first polished surface.

26. The circuit of claim 21, further including a conductive interconnect which extends between the interconnect region and second polished surface.

27. The circuit of claim 26, further including dielectric material which extends between the conductive interconnect and first bonding layer.

28. The circuit of claim 21, wherein the donor layer includes an isolation region which extends through the second polished surface.

29. The circuit of claim 20, wherein the first electronic device is a vertically oriented semiconductor device.

30. The circuit of claim 29, wherein the first electronic device is bonded to the donor layer through a second bonding layer.

31. The circuit of claim 29, wherein the first electronic device includes a stack of crystalline semiconductor layers.

32. The circuit of claim 31, wherein the first electronic device includes a mesa structure which includes the stack.

33. The circuit of claim 20, further including a capacitor connected to the first electronic device.

59. A semiconductor circuit, comprising:

a carrier substrate;

an interconnect region carried by the carrier substrate;

a first bonding layer which includes electrically conductive material;

a donor layer coupled to the interconnect region through the first bonding layer, wherein the donor layer has a graded doping concentration; and

an electronic device carried by the donor layer.

60. The circuit of claim 59, wherein the carrier substrate includes semiconductor material.

61. The circuit of claim 59, wherein the carrier substrate carries a transistor in communication with the electronic device through the interconnect region.

62. The circuit of claim 59, wherein the carrier substrate includes CMOS circuitry in communication with the electronic device through the interconnect region.

63. The circuit of claim 59, wherein the donor substrate includes semiconductor material.

64. The circuit of claim 59, wherein the first bonding layer consists essentially of a metal.

65. The circuit of claim 59, wherein the donor layer includes first and second opposed polished surfaces.

66. The circuit of claim 65, wherein the doping concentration of the donor layer is greater proximate to the first polished surface than the second polished surface.