Memory cell comprising switchable semiconductor memory element with trimmable resistance

• US 7,800,932 B2
• Filed: 09/28/2005
• Issued: 09/21/2010
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Kumar, Tanmay, Herner, S. Brad
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/237,167
• Publication Number:
  US 20070090425A1
• Time in Patent Office: 1,819 Days
• Field of Search: 365/158, 365/171, 365/173, 365/148, 365/163, 365/175, 438/3, 361/58, 361/71, 361/73, 257/295
• US Class Current: 365/148
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/884 based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883

Abstract

A nonvolatile memory cell comprising doped semiconductor material and a diode can store memory states by changing the resistance of the doped semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) Set pulses are of short duration and above a threshold voltage, while reset pulses are longer duration and below a threshold voltage. In some embodiments multiple resistance states can be achieved, allowing for a multi-state cell, while restoring a prior high-resistance state allows for an rewriteable cell. In some embodiments, the diode and a switchable memory formed of doped semiconductor material are formed in series, while in other embodiments, the diode itself serves as the semiconductor switchable memory element.

Claims

1. A method for changing and sensing data states for a nonvolatile memory cell, the method comprising:

switching silicon or a silicon alloy, or germanium or a germanium alloy semiconductor material of a semiconductor diode from a first stable resistivity state to a second stable resistivity state, the second resistivity state lower resistivity than the first resistivity state;

switching the silicon or a silicon alloy, or germanium or a germanium alloy semiconductor material of the semiconductor diode from the second stable resistivity state to a third stable resistivity state, the third resistivity state higher resistivity than the second resistivity state; and

sensing the first resistivity state, the second resistivity state, or the third resistivity state as a data state of the memory cell,

wherein;

the semiconductor diode consists essentially of the silicon or silicon alloy, or germanium or germanium alloy semiconductor material;

at least a portion of the silicon or silicon alloy, or germanium or germanium alloy semiconductor material is doped;

the memory cell comprises a portion of a first conductor;

a portion of a second conductor; and

a switchable memory element comprising the silicon or silicon alloy, or germanium or germanium alloy semiconductor material of the semiconductor diode, the switchable memory element disposed between the first and second conductors;

the semiconductor diode in the first stable resistivity state has a first resistivity when a read voltage is applied to the semiconductor diode;

the semiconductor diode in the second stable resistivity state has a second resistivity when the read voltage is applied to the semiconductor diode;

the semiconductor diode in the third stable resistivity state has a third resistivity when the read voltage is applied to the semiconductor diode; and

the first resistivity, the second resistivity, and the third resistivity are different from each other.

2. The method of claim 1 wherein the difference in resistivity between the first resistivity state and the second resistivity state is at least a factor of two.

3. The method of claim 1 wherein the difference in resistivity between the first resistivity state and the second resistivity state is at least a factor of ten.

4. The method of claim 1 wherein the at least a portion of the silicon or silicon alloy, or germanium or germanium alloy semiconductor material is doped with a p-type or n-type dopant.

5. The method of claim 1 wherein the second conductor is disposed above the first conductor, the switchable memory element vertically disposed between the first conductor and the second conductor.

6. The method of claim 1 wherein switching from the first resistivity state to the second resistivity state is achieved by applying to the switchable memory element a first electrical pulse having a first electrical amplitude and a first pulse width.

7. The method of claim 6 wherein, after switching to the second resistivity state, application of a second electrical pulse having a second electrical amplitude and a second pulse width, the second electrical amplitude no more than 120 percent of the first electrical amplitude, does not cause switching to a higher resistivity state.

8. The method of claim 6 wherein switching from the second resistivity state to the third resistivity state is achieved by application of a third electrical pulse having a third electrical amplitude and a third width, wherein the third width is at least five times the second width.

9. The method of claim 8 wherein the first pulse width is about 5 msec or less.

10. The method of claim 8 wherein the third pulse width is about 25 msec or greater.

11. The method of claim 1 wherein:

the silicon or silicon alloy, or germanium or germanium alloy semiconductor material is a doped polycrystalline material that comprises a plurality of grain boundaries;

at least some dopant atoms move away from at least some of the plurality of grain boundaries, during switching the silicon or silicon alloy, or germanium or germanium alloy semiconductor material from the first stable resistivity state to the second stable resistivity state; and

at least some of the dopant atoms move to at least some of the plurality of grain boundaries, during switching the silicon or silicon alloy, or germanium or germanium alloy semiconductor material from the second stable resistivity state to the third stable resistivity state.

12. The method of claim 1 wherein:

the silicon or silicon alloy, or germanium or germanium alloy semiconductor material is a polycrystalline material having a degree of order;

the degree of order increases during switching the silicon or silicon alloy, or germanium or germanium alloy semiconductor material from the first stable resistivity state to the second stable resistivity state; and

the degree of order decreases during switching the silicon or silicon alloy, or germanium or germanium alloy semiconductor material from the second stable resistivity state to the third stable resistivity state.

13. A method for changing data states for a nonvolatile memory cell, the method comprising:

switching silicon or a silicon alloy, or germanium or a germanium alloy semiconductor material of a semiconductor diode from a first stable resistivity state to a second stable resistivity state, the second resistivity state lower resistivity than the first resistivity state, and

switching the silicon or a silicon alloy, or germanium or a germanium alloy semiconductor material of the semiconductor diode from the second resistivity state to a third stable resistivity state, the third resistivity state lower resistivity than the second resistivity state,

wherein;

the semiconductor diode consists essentially of the silicon or silicon alloy, or germanium or germanium alloy semiconductor material;

at least some portion of the silicon or silicon alloy, or germanium or germanium alloy semiconductor material is doped;

the memory cell consists of a portion of a first conductor;

a portion of a second conductor; and

the semiconductor diode that functions as a switchable memory element, disposed between the portion of the first conductor and the portion of the second conductor;

the semiconductor diode in the first stable resistivity state has a first resistivity when a read voltage is applied to the semiconductor diode;

the semiconductor diode in the second stable resistivity state has a second resistivity when the read voltage is applied to the semiconductor diode;

the semiconductor diode in the third stable resistivity state has a third resistivity when the read voltage is applied to the semiconductor diode; and

the first resistivity, the second resistivity, and the third resistivity are different from each other.

14. The method of claim 13 further comprising sensing the first resistivity state, the second resistivity state, or the third resistivity state as a data state of the memory cell.

15. The method of claim 13 wherein the memory cell is within a memory array, and wherein the memory array is a monolithic three dimensional memory array comprising at least two memory levels formed above a substrate.

16. The method of claim 13 wherein the step of switching the silicon or silicon alloy, or germanium or germanium alloy semiconductor material from the first resistivity state to the second resistivity state comprises applying to the switchable memory element a first electrical pulse having a first electrical amplitude and a first pulse width, and wherein the step of switching the silicon or silicon alloy, or germanium or germanium alloy semiconductor material from the second resistivity state to the third resistivity state comprises applying to the switchable memory element a second electrical pulse having a second electrical amplitude and a second width, the second electrical amplitude greater than the first electrical amplitude.

17. The method of claim 13 wherein the semiconductor diode is a junction diode.

18. The method of claim 13 wherein:

the silicon or silicon alloy, or germanium or germanium alloy semiconductor material is a doped polycrystalline material that comprises a plurality of grain boundaries; and

at least some dopant atoms move away from at least some of the plurality of grain boundaries, during switching the silicon or silicon alloy, or germanium or germanium alloy semiconductor material from the first stable resistivity state to the second stable resistivity state.

19. The method of claim 13 wherein:

the silicon or silicon alloy, or germanium or germanium alloy semiconductor material is a polycrystalline material having a degree of order;

the degree of order increases during switching the silicon or silicon alloy, or germanium or germanium alloy semiconductor material from the first stable resistivity state to the second stable resistivity state; and

the degree of order increases during switching the silicon or silicon alloy, or germanium or germanium alloy semiconductor material from the second stable resistivity state to the third stable resistivity state.