Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance

• US 7,800,933 B2
• Filed: 07/31/2006
• Issued: 09/21/2010
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Kumar, Tanmay, Herner, S. Brad, Petti, Christopher J, Scheuerlein, Roy E
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/496,986
• Publication Number:
  US 20070072360A1
• Time in Patent Office: 1,513 Days
• Field of Search: 365/158, 365/171, 365/173, 365/148, 365/163, 365/230.06, 365/175, 438/3, 438/1, 257/296, 257/3, 257/295
• US Class Current: 365/148
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.

Claims

1. A method for changing and sensing data states for a nonvolatile memory cell, the method comprising:

switching semiconductor material from a first stable resistivity state to a second stable resistivity state, the second resistivity state lower resistivity than the first resistivity state;

switching the semiconductor material from the second stable resistivity state to a third stable resistivity state, the third resistivity state higher resistivity than the second resistivity state; and

sensing the third resistivity state as a data state of the memory cell,

wherein;

the memory cell comprises a portion of a first conductor, a portion of a second conductor, and a switchable memory element comprising the semiconductor material,

the semiconductor material is selected from silicon, germanium, or an alloy of silicon and/or germanium,

the switchable memory element is disposed between the first and second conductors,

the semiconductor material in the first stable resistivity state has a first resistivity when a read voltage is applied to the semiconductor material;

the semiconductor material in the second stable resistivity state has a second resistivity when the read voltage is applied to the semiconductor material;

the semiconductor material in the third stable resistivity state has a third resistivity when the read voltage is applied to the semiconductor material;

the first resistivity, the second resistivity, and the third resistivity are different from each other;

the semiconductor material is a doped polycrystalline material that comprises a plurality of grain boundaries;

at least some dopant atoms move away from at least some of the plurality of grain boundaries, during switching the semiconductor material from the first stable resistivity state to the second stable resistivity state; and

at least some of the dopant atoms move to at least some of the plurality of grain boundaries, during switching the semiconductor material from the second stable resistivity state to the third stable resistivity state.

2. The method of claim 1 wherein the difference in resistivity between the first resistivity state and the third resistivity state is at least a factor of two.

3. The method of claim 1 wherein the difference in resistivity between the first resistivity state and the third resistivity state is at least a factor of five.

4. The method of claim 1 wherein at least a portion of the semiconductor material is doped with a p-type or n-type dopant.

5. The method of claim 1 wherein the second conductor is disposed above the first conductor, the switchable memory element vertically disposed between the first conductor and the second conductor.

6. The method of claim 1 wherein the memory cell further comprises a diode, the diode disposed between the first and second conductors.

7. The method of claim 6 wherein the switchable memory element is in series with the diode.

8. The method of claim 6 wherein the switchable memory element comprises the diode, the diode comprising the semiconductor material.

9. The method of claim 8 wherein the diode is a vertically oriented semiconductor junction diode.

10. The method of claim 9 wherein the diode is a p-i-n diode.

11. The method of claim 9 wherein the diode is a p-n diode.

12. The method of claim 8 wherein the semiconductor material is polycrystalline or microcrystalline.

13. The method of claim 1 wherein switching from the first resistivity state to the second resistivity state is achieved by applying to the switchable memory element a first electrical pulse having a first amplitude and a first polarity.

14. The method of claim 13 wherein switching from the second resistivity state to the third resistivity state is achieved by application of a second electrical pulse having a second amplitude and a second polarity, the second polarity opposite the first polarity.

15. The method of claim 1 wherein the nonvolatile memory cell resides in a first memory level of a monolithic three dimensional memory array, the first memory level monolithically formed above a substrate, wherein at least a second memory level is monolithically formed above the first memory level.

16. The method of claim 1 wherein the semiconductor material is a polycrystalline material having a degree of order that changes during switching the semiconductor material from the first stable resistivity state to the second stable resistivity state.

17. A method for changing and sensing data states for a nonvolatile memory cell, the method comprising:

switching semiconductor material from a first stable resistivity state to a second stable resistivity state, the second resistivity state lower resistivity than the first resistivity state;

switching the semiconductor material from the second stable resistivity state to a third stable resistivity state, the third resistivity state higher resistivity than the second resistivity state;

switching the semiconductor material from the third stable resistivity state to a fourth stable resistivity state, the fourth resistivity state lower resistivity than the third resistivity state; and

sensing the fourth resistivity state as a data state of the memory cell,

wherein;

the memory cell comprises a portion of a first conductor, a portion of a second conductor, and a switchable memory element comprising the semiconductor material,

the semiconductor material is selected from silicon, germanium, or an alloy of silicon and/or germanium,

the switchable memory element is disposed between the first and second conductors,

the semiconductor material in the first stable resistivity state has a first resistivity when a read voltage is applied to the semiconductor material;

the semiconductor material in the second stable resistivity state has a second resistivity when the read voltage is applied to the semiconductor material;

the semiconductor material in the third stable resistivity state has a third resistivity when the read voltage is applied to the semiconductor material;

the semiconductor material in the fourth stable resistivity state has a fourth resistivity when the read voltage is applied to the semiconductor material; and

the first resistivity, the second resistivity, the third resistivity, and the fourth resistivity are different from each other;

the semiconductor material is a doped polycrystalline material that comprises a plurality of grain boundaries;

at least some dopant atoms move away from at least some of the plurality of grain boundaries, during switching the semiconductor material from the first stable resistivity state to the second stable resistivity state; and

at least some of the dopant atoms move to at least some of the plurality of grain boundaries, during switching the semiconductor material from the second stable resistivity state to the third stable resistivity state.

18. The method of claim 17 further comprising:

switching the semiconductor material from the fourth stable resistivity state to a fifth stable resistivity state, the fifth resistivity state higher resistivity than the fourth resistivity state; and

sensing the fifth resistivity state as a data state of the memory cell.

19. The method of claim 17 further comprising sensing the third resistivity state as a data state of the memory cell.

20. The method of claim 17 wherein the memory cell comprises a diode.

21. The method of claim 20 wherein the diode comprises the semiconductor material, and wherein the semiconductor material is polycrystalline or microcrystalline.

22. The method of claim 21 wherein the diode is a vertically oriented semiconductor junction diode.

23. The method of claim 22 wherein the memory cell resides in a first memory level of a monolithic three dimensional memory array, the first memory level monolithically formed above a substrate, wherein at least a second memory level is monolithically formed above the first memory level.

24. The method of claim 23 wherein the substrate comprises monocrystalline silicon.

25. The method of claim 17 wherein the semiconductor material is a polycrystalline material having a degree of order that changes during switching the semiconductor material from the first stable resistivity state to the second stable resistivity state.

26. A method for changing and sensing data states for a nonvolatile memory cell, the nonvolatile memory cell comprising a polycrystalline or microcrystalline semiconductor junction diode comprising semiconductor material selected from silicon, germanium, or an alloy of silicon and/or germanium, the diode disposed between a first conductor and a second conductor, the method comprising:

switching the semiconductor material from a first resistivity state to a second resistivity state, the second resistivity state lower resistivity than the first resistivity state;

switching the semiconductor material from the second resistivity state to a third resistivity state, the third resistivity state higher resistivity than the second resistivity state; and

sensing the third resistivity state as a data state of the memory cell,

the semiconductor material in the first stable resistivity state has a first resistivity when a read voltage is applied to the semiconductor material;

the semiconductor material in the second stable resistivity state has a second resistivity when the read voltage is applied to the semiconductor material;

the semiconductor material in the third stable resistivity state has a third resistivity when the read voltage is applied to the semiconductor material; and

the first resistivity, the second resistivity, and the third resistivity are different from each other;

the semiconductor material is a doped polycrystalline material that comprises a plurality of grain boundaries;

at least some dopant atoms move away from at least some of the plurality of grain boundaries, during switching the semiconductor material from the first stable resistivity state to the second stable resistivity state; and

at least some of the dopant atoms move to at least some of the plurality of grain boundaries, during switching the semiconductor material from the second stable resistivity state to the third stable resistivity state.

27. The method of claim 26 wherein switching from the first resistivity state to the second resistivity state is achieved by applying a first electrical pulse between the first conductor and the second conductor, the first electrical pulse having a first amplitude and a first polarity.

28. The method of claim 27 wherein the nonvolatile memory cell further comprises a dielectric rupture antifuse disposed between the first conductor and the second conductor, and wherein the first electrical pulse ruptures the dielectric rupture antifuse.

29. The method of claim 27 wherein switching from the second resistivity state to the third resistivity state is achieved by applying a second electrical pulse between the first conductor and the second conductor, the second electrical pulse having a second amplitude and a second polarity.

30. The method of claim 29 wherein the second polarity is opposite the first polarity.

31. The method of claim 30 wherein, during application of the first electrical pulse, the diode is forward biased, and wherein, during application of the second electrical pulse, the diode is reverse biased.

32. The method of claim 31 further comprising switching the semiconductor material from the third resistivity state to a fourth resistivity state, the fourth resistivity state lower resistivity than the third resistivity state.

33. The method of claim 32 wherein switching from the third resistivity state to the fourth resistivity state is achieved by applying a third electrical pulse between the first conductor and the second conductor, the third electrical pulse having a third amplitude and a third polarity.

34. The method of claim 33 wherein the third polarity is opposite the second polarity.

35. The method of claim 34,

wherein, before application of the first electrical pulse, a first current flows between the first conductor and the second conductor when a read voltage is applied between the first conductor and the second conductor, and

wherein, after application of the first electrical pulse and before application of the second electrical pulse, a second current flows between the first conductor and the second conductor when the read voltage is applied between the first conductor and the second conductor, and

wherein, after application of the second electrical pulse and before application of the third electrical pulse, a third current flows between the first conductor and the second conductor when the read voltage is applied between the first conductor and the second conductor, and

wherein, after application of the third electrical pulse, a fourth current flows between the first conductor and the second conductor when the read voltage is applied between the first conductor and the second conductor,

wherein the third current is at least three times the first current,

wherein the fourth current is at least three times the third current, and

wherein the second current is at least three times the fourth current.

36. The method of claim 29,

wherein, before application of the first electrical pulse, a first current flows between the first conductor and the second conductor when a read voltage is applied between the first conductor and the second conductor, and

wherein, after application of the first electrical pulse and before application of the second electrical pulse, a second current flows between the first conductor and the second conductor when the read voltage is applied between the first conductor and the second conductor, and

wherein, after application of the second electrical pulse, a third current flows between the first conductor and the second conductor when the read voltage is applied between the first conductor and the second conductor,

wherein the third current is at least three times the first current, and

wherein the second current is at least three times the third current.

37. The method of claim 36 wherein the second polarity is opposite the first polarity.

38. The method of claim 26 wherein the semiconductor material is a polycrystalline material having a degree of order that changes during switching the semiconductor material from the first stable resistivity state to the second stable resistivity state.

39. A method for programming and sensing a rewriteable memory cell, the method comprising:

switching semiconductor material from a first stable resistivity state to a second stable resistivity state, the second resistivity state lower resistivity than the first resistivity state;

switching the semiconductor material from the second stable resistivity state to a third stable resistivity state, the third resistivity state lower resistivity than the second resistivity state; and

sensing the third resistivity state as a data state of the memory cell,

wherein;

the memory cell comprises a portion of a first conductor, a portion of a second conductor, and a switchable memory element comprising the semiconductor material,

the semiconductor material is selected from silicon, germanium, or an alloy of silicon and/or germanium,

the switchable memory element is disposed between the first and second conductors,

the semiconductor material in the first stable resistivity state has a first resistivity when a read voltage is applied to the semiconductor material;

the semiconductor material in the second stable resistivity state has a second resistivity when the read voltage is applied to the semiconductor material;

the semiconductor material in the third stable resistivity state has a third resistivity when the read voltage is applied to the semiconductor material; and

the first resistivity, the second resistivity, and the third resistivity are different from each other;

the semiconductor material is a doped polycrystalline material that comprises a plurality of grain boundaries; and

at least some dopant atoms move away from at least some of the plurality of grain boundaries, during switching the semiconductor material from the first stable resistivity state to the second stable resistivity state.

40. The method of claim 39 wherein the semiconductor material is polycrystalline or microcrystalline.

41. The method of claim 40 wherein the switchable memory element comprises a diode, the diode comprising the semiconductor material.

42. The method of claim 40 wherein the step of switching the semiconductor material from the first resistivity state to the second resistivity state comprises applying a first electrical pulse between the first conductor and the second conductor, the first electrical pulse having a first polarity.

43. The method of claim 42 wherein the step of switching the semiconductor material from the second resistivity state to the third resistivity state comprises applying a second electrical pulse between the first conductor and the second conductor, the second electrical pulse having a second polarity.

44. The method of claim 43 wherein the second polarity is opposite the first polarity.

45. The method of claim 44 wherein, during the first electrical pulse, the diode is forward biased, and, during the second electrical pulse, the diode is reverse biased.

46. The method of claim 41 wherein the diode is a semiconductor junction diode.

47. The method of claim 46 wherein the semiconductor junction diode is vertically oriented.

48. The method of claim 47 wherein the diode is a p-i-n diode.

49. The method of claim 47 wherein the diode is a p-n diode.

50. The method of claim 39 wherein the semiconductor material is a polycrystalline material having a degree of order that changes during switching the semiconductor material from the first stable resistivity state to the second stable resistivity state.