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Multi-pair gigabit ethernet transceiver

  • US 7,801,240 B2
  • Filed: 11/18/2008
  • Issued: 09/21/2010
  • Est. Priority Date: 11/09/1998
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit communication device comprising:

  • a decoder circuit operable to receive and decode at least one intersymbol interference (ISI) compensated signal sample, and to generate tentative decisions and a final decision; and

    a decision feedback equalizer coupled in feedback fashion to the decoder circuit, the decision feedback equalizer including a set of low-ordered coefficients and a set of high-ordered coefficients, the decision feedback equalizer operable to generate a first digital signal that is partially ISI-compensated based on the tentative decisions and the high-ordered coefficients; and

    a multiple-decision feedback equalizer operable to generate at least one ISI-compensated signal based on the partially ISI-compensated signal and the low-ordered coefficients, and to provide the at least one ISI-compensated signal to the decoder circuit.

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