Communication steering for use in a multi-master shared resource system

• US 7,802,038 B2
• Filed: 11/21/2008
• Issued: 09/21/2010
• Est. Priority Date: 10/09/2003
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Cruz, Arnold R., Bedwell, Ryan D., Moyer, William C., Vaglica, John J.
• Primary Examiner(s): Rinehart; Mark
• Assistant Examiner(s): Patel; Nimesh G
• Application Number:
  US12/276,038
• Publication Number:
  US 20090077291A1
• Time in Patent Office: 669 Days
• Field of Search: 710/110, 710/260, 710/266
• US Class Current: 710/110
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.

Claims

1. A data processing system, comprising:

a system bus;

a first bus master coupled to the system bus;

a second bus master coupled to the system bus; and

a resource coupled to the system bus and useable by the first bus master and the second bus master,

wherein the resource comprises;

endpoint storage circuitry comprising a plurality of endpoints, wherein each of the plurality of endpoints is allocatable to at least one of the first bus master and the second bus master, and wherein allocatability of each of the plurality of endpoints is programmable, and

wherein the resource further comprises;

a controller, coupled to the endpoint storage circuitry, the controller comprising;

interrupt steering resisters; and

interrupt steering logic, wherein the interrupt steering logic routes interrupts to a corresponding one of the first bus master and the second bus master based on steering information provided by the interrupt steering registers, and wherein the plurality of endpoints are allocated based on the interrupt steering registers,

steering logic for establishing a communication path between the resource and at least one of the first and second bus masters, wherein the communication path is determined by the programmable circuit in the resource, and

wherein no additional steering logic is required in the communication path between the resource and the at least one of the first and second bus masters; and

a conductor for transferring an additional signal, separate from the system bus, between the resource and the at least one of the first and second bus masters via the communication path.

2. The data processing system as in claim 1, wherein for each of the plurality of endpoints, the interrupt steering registers indicate allocation to one of the first bus master and the second bus master.

3. The data processing system as in claim 1, wherein the interrupt steering registers comprise an interrupt steering set register and an interrupt steering clear register.

4. The data processing system as in claim 3, wherein the interrupt steering registers further comprise interrupt steering storage circuitry coupled to the interrupt steering set register and the interrupt steering clear register, the interrupt steering storage circuitry providing the steering information to the interrupt steering logic.

5. The data processing system as in claim 4, wherein the interrupt steering storage circuitry comprises a plurality of set-reset latches.

6. A method, comprising:

providing a first bus master coupled to a system bus;

providing a second bus master coupled to the system bus;

providing a resource coupled to the system bus;

providing a programmable circuit in the resource, wherein the resource comprises;

endpoint storage circuitry comprising a plurality of endpoints,

wherein each of the plurality of endpoints is allocatable to at least one of the first bus master and the second bus master, and wherein allocatability of each of the plurality of endpoints is programmable, and wherein the programmable circuit further comprises;

interrupt steering registers, and

interrupt steering logic, wherein the interrupt steering logic routes interrupts to a corresponding one of the first bus master and the second bus master based on steering information provided by the interrupt steering registers, and wherein the plurality of endpoints are allocated based on the interrupt steering registers;

establishing a communication path between the resource and at least one of the first and second bus masters,

wherein the communication path is determined by the programmable circuit in the resource, and

wherein no additional steering logic is required in the communication path between the resource and the at least one of the first and second bus masters; and

transferring an additional signal, separate from the system bus, between the resource and the at least one of the first and second bus masters via the communication path.

7. The method as in claim 6, wherein the additional signal comprises an interrupt signal.

8. The method as in claim 6, wherein the additional signal comprises a DMA signal.

9. The method as in claim 6, wherein the additional signal comprises a reset signal.

10. The method as in claim 6, wherein the additional signal comprises a power control signal.

11. The method as in claim 6, further comprising:

allowing the first bus master to program a set register during a first bus cycle of the system bus; and

allowing the second bus master to program a clear register during a second bus cycle of the system bus, wherein the second bus cycle is subsequent to the first bus cycle.

12. The method as in claim 6, wherein the first bus master and the second bus master share control of the programmable circuit in the resource.

13. The method as in claim 6, wherein transferring of the additional signal is not aborted because the resource is disowned by the first and second bus masters.

14. A data processing system, comprising:

a first bus master coupled to a system bus;

a second bus master coupled to the system bus;

a resource coupled to the system bus, the resource comprising;

a programmable circuit,

endpoint storage circuitry comprising a plurality of endpoints,

wherein each of the plurality of endpoints is allocatable to at least one of the first bus master and the second bus master, and wherein allocatability of each of the plurality of endpoints is programmable, and wherein the programmable circuit further comprises;

interrupt steering registers, and

interrupt steering logic, wherein the interrupt steering logic routes interrupts to a corresponding one of the first bus master and the second bus master based on steering information provided by the interrupt steering registers, and wherein the plurality of endpoints are allocated based on the interrupt steering registers; and

steering logic for establishing a communication path between the resource and at least one of the first and second bus masters,

wherein the communication path is determined by the programmable circuit in the resource, and

wherein no additional steering logic is required in the communication path between the resource and the at least one of the first and second bus masters; and

a conductor for transferring an additional signal, separate from the system bus, between the resource and the at least one of the first and second bus masters via the communication path.