Flash memory system control scheme

• US 7,802,064 B2
• Filed: 03/29/2007
• Issued: 09/21/2010
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Elmore; Stephen C
• Assistant Examiner(s): Giardino, Jr.; Mark A
• Application Number:
  US11/693,027
• Publication Number:
  US 20070233939A1
• Time in Patent Office: 1,272 Days
• Field of Search: 711/103, 711/167, 711/157
• US Class Current: 711/157
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
• CPC Class Codes: G11C 2216/24 Nonvolatile memory in which programming can be carried out in one memory bank or array whilst a word or sector in another bank or array is being erased simultaneously
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Abstract

A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.

Claims

1. A method for high speed wear leveling programming in a Flash memory system having a plurality Flash memory devices, comprising:

i) receiving a data file having k pages, k being an integer greater than 0;

ii) selecting a programming profile corresponding to the size of k and configuration parameters of the Flash memory system by calculating a ceiling function of z=k/i, the configuration parameters including j Flash memory devices where each of the j Flash memory devices have i pages per block, where j and i are integer values greater than 0;

iii) programming at least one of the k pages of the data file in each of at least two of the plurality of Flash memory devices in accordance with the programming profile including a multiple file structure when z is greater than j, the multiple file structure including storing m units of j*i pages of the data file in j Flash memory devices, and storing k−

(m*(j*i)) pages of the data file in z of j Flash memory devices when z is less than or equal to j, where m is an integer value greater than 0.

2. The method of claim 1, wherein the step of programming includes sequentially providing program commands to each of the j Flash memory devices for programming the j*i pages of the data file, each program command for programming the at least one of the k pages.

3. The method of claim 2, wherein the step of programming includes sequentially providing program commands to each of the z Flash memory devices for programming the k−

(m*(j*i)) pages, each program command for programming the at least one of the k pages.

4. The method of claim 1, wherein the at least two of the plurality of Flash memory devices are serially connected to each other.

5. The method of claim 4, wherein a first Flash memory device of the at least two of the plurality of Flash memory devices executes a first programming operation in response to a first command, and a second Flash memory device of the at least two of the plurality of Flash memory devices initiates a second programming operation in response to a second command while the first Flash memory device is executing the first operation.

6. The method of claim 5, wherein the second command is passed to the second Flash memory device through the first Flash memory device before the second Flash memory device initiates the second programming operation.