Superscalar RISC instruction scheduling

• US 7,802,074 B2
• Filed: 04/02/2007
• Issued: 09/21/2010
• Est. Priority Date: 03/31/1992
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Iadonato, Kevin Ray, Wang, Johannes, Nguyen, Le Trong, Garg, Sanjiv
• Primary Examiner(s): DONAGHUE, LARRY D
• Application Number:
  US11/730,566
• Publication Number:
  US 20080059770A1
• Time in Patent Office: 1,268 Days
• Field of Search: 712/23, 712/218, 712/217, 712/216
• US Class Current: 712/23
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags

Abstract

A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

Claims

1. A system, comprising:

a data-dependency checker configured to provide data-dependency results indicating a dependency between one or more instructions in an instruction window; and

tag-assignment logic configured to receive the data-dependency results from the data-dependency checker and to output a tag in place of a register address for an operand of a first instruction if the first instruction is dependent on a previous instruction in the instruction window, wherein the tag comprises an address of the operand.

2. The system of claim 1, further comprising:

a plurality of multiplexers configured to transfer execution results from storage locations in a temporary buffer to register-file locations in-order based on an order of instructions in the instruction window.

3. The system of claim 2, wherein the plurality of multiplexers simultaneously transfer a group of execution results from the temporary buffer to the register-file locations.

4. The system of claim 2, wherein the plurality of multiplexers transfers an execution result for an instruction of a group of instructions in the instruction window from the temporary buffer to the register file when all execution results for all prior instructions of the group of instructions are retirable.

5. The system of claim 1, wherein the tag further comprises a 1-bit identifier that indicates whether the address within the tag is a register-file address or a temporary-buffer address.

6. The system of claim 1, wherein the data-dependency checker is further configured to compare a source-register address of each instruction in the instruction window to a destination-register address of each previous instruction in the instruction window.

7. A computer system, comprising:

a memory unit configured to store instructions;

a bus coupled to the memory unit and configured to retrieve the instructions; and

a processor coupled to the bus, wherein the processor comprises a register-renaming system, comprising;

a data-dependency checker configured to provide data-dependency results indicating a dependency between one or more instructions in an instruction window; and

tag-assignment logic configured to receive the data-dependency results from the data-dependency checker and to output a tag in place of a register address for an operand of a first instruction if the first instruction is dependent on a previous instruction in the instruction window, wherein the tag comprises an address of the operand.

8. The computer system of claim 7, wherein the processor further comprises:

a plurality of multiplexers configured to transfer execution results from storage locations in a temporary buffer to register-file locations in-order based on an order of instructions in the instruction window.

9. The computer system of claim 8, wherein the plurality of multiplexers simultaneously transfer a group of execution results from the temporary buffer to the register-file locations.

10. The computer system of claim 8, wherein the plurality of multiplexers transfers an execution result for an instruction of a group of instructions in the instruction window from the temporary buffer to the register file when all execution results for all prior instructions of the group of instructions are retirable.

11. The computer system of claim 7, wherein the tag further comprises a 1-bit identifier that indicates whether the address within the tag is a register-file address or a temporary-buffer address.

12. The computer system of claim 7, wherein the data-dependency checker is further configured to compare a source-register address of each instruction in the instruction window to a destination-register address of each previous instruction in the instruction window.

13. A register-renaming method, comprising:

providing data-dependency results that indicate a dependency between one or more instructions in an instruction window; and

outputting a tag in place of a register address for an operand of a first instruction if the first instruction is dependent, as indicated by the data-dependency results, on a previous instruction in the instruction window, wherein the tag comprises an address of the operand.

14. The register-renaming method of claim 13, further comprising:

transferring execution results from storage locations in a temporary buffer to register-file locations in-order based on an order of instructions in the instruction window.

15. The register-renaming method of claim 14, wherein the transferring execution results from storage locations in a temporary buffer to register-file locations in-order based on an order of instructions in the instruction window comprises:

simultaneously transferring a group of execution results from the temporary buffer to the register-file locations.

16. The register-renaming method of claim 14, wherein the transferring execution results from storage locations in a temporary buffer to register-file locations in-order based on an order of instructions in the instruction window comprises:

transferring an execution result for an instruction of a group of instructions in the instruction window from the temporary buffer to the register file when all execution results for all prior instructions of the group of instructions are retirable.

17. The register-renaming method of claim 13, wherein the tag further comprises a 1-bit identifier that indicates whether the address within the tag is a register-file address or a temporary-buffer address.

18. The register-renaming method of claim 13, wherein the providing data-dependency results that indicate any dependencies between instructions in an instruction window further comprises:

comparing a source-register address of each instruction in the instruction window to a destination-register address of each previous instruction in the instruction window.