Functional block level clock-gating within a graphics processor

• US 7,802,118 B1
• Filed: 12/21/2006
• Issued: 09/21/2010
• Est. Priority Date: 12/21/2006
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Abdalla, Karim M., Hasslen, Robert J. III
• Primary Examiner(s): Patel; Nitin C
• Application Number:
  US11/614,248
• Time in Patent Office: 1,370 Days
• Field of Search: 713/322, 713/500
• US Class Current: 713/322
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An embodiment of the invention includes receiving an indicator of a flow of data associated with a graphics processing stage within a graphics pipeline of a graphics processor. A clock signal to a portion of the graphics processing stage is modified based on a status of the flow of data. The clock signal is received from a clock signal generator within the graphics processor.

Claims

1. A method, comprising:

receiving an indicator of an activity-level of each of a plurality of graphics processing stages within a graphics processor indicative of a data flow, the graphics processing stages being included in a graphics processing pipeline, each graphics processing stage from the plurality being configured to receive a clock signal from a clock signal generator;

determining a status of each of the plurality of graphics processing stages based on the indicator of the activity-level;

disabling the clock signal to at least a portion of a particular graphics processing stage when the status indicates that the particular graphics processing stage is an inactive status and disabling said at least a portion of the particular graphics processing stage for at least one clock cycle saves power without significantly affecting processing performance of the graphics processing pipeline;

determining the status of the graphics processing stage during a pulse wake-up time period in response to a wake-up signal; and

sending an indicator of the status to at least one of an upstream circuit component within the graphics processing pipeline or a downstream component within the graphics processing pipeline.