Encoding and decoding apparatus and method with hamming weight enhancement

• US 7,802,151 B1
• Filed: 11/30/2006
• Issued: 09/21/2010
• Est. Priority Date: 03/07/2001
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Pantas, Doan, Toai
• Primary Examiner(s): Torres; Joseph D
• Application Number:
  US11/606,677
• Time in Patent Office: 1,391 Days
• Field of Search: 714/701, 714/776, 714/809
• US Class Current: 714/701
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/31 combining coding for error detection or correction and efficient use of the spectrum without error detection or correction H03M5/14 , H03M5/145
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Abstract

A communication decoding method comprises receiving processed binary data including a binary code word and an indication of whether bits of the binary code word are inverted and inverting each bit of the binary code word if the indication indicates that the bits are inverted.

Claims

1. A communication decoding method, comprising:

receiving processed binary data, the processed binary data including a binary code word and an indication of whether bits of the binary code word are inverted, the binary code word including a first portion and a second portion;

inverting each bit of only the first portion of the binary code word when the indication indicates that the bits are inverted; and

performing run length limited (RLL) decoding on only the second portion of the binary code word.

2. The method of claim 1, wherein the indication comprises a binary digit having (i) a first value when the bits of the binary code word are inverted and (ii) having a second value otherwise.

3. The method of claim 1, further comprising performing at least one of error correction decoding and reverse precoding of the binary code word.

4. A communication decoder, comprising:

a memory to receive processed binary data, the processed binary data including a binary code word and an indication of whether bits of the binary code word are inverted, the binary code word including a first portion and a second portion; and

a processor to;

invert each bit of only the first portion of the binary code word when the indication indicates that the bits are inverted, and

run length limited (RLL) decode only the second portion of the binary code word.

5. The decoder of claim 4, wherein the indication comprises a binary digit (i) having a first value when the bits of the binary code word are inverted and (ii) having a second value otherwise.

6. The decoder of claim 4, further comprising performing at least one of error correction decoding and reverse precoding of the binary code word.

7. A non-transitory computer-readable medium having stored thereon:

a first set of machine-executable instructions for receiving processed binary data, the processed binary data including a binary code word and an indication of whether bits of the binary code word are inverted, the binary code word including a first portion and a second portion;

a second set of machine-executable instructions for inverting each bit of only the first portion of the binary code word when the indication indicates that the bits are inverted; and

a third set of machine-executable instructions for performing run length limited (RLL) decoding on only the second portion of the binary code word.

8. The computer-readable medium of claim 7, wherein the indication comprises a binary digit (i) having a first value when the bits of the binary code word are inverted and (ii) having a second value otherwise.

9. The computer-readable medium of claim 7, further having stored thereon a fourth set of machine-executable instructions for performing at least one of error correction decoding and reverse precoding of the binary code word.

10. A communication decoder, comprising:

receiving means for receiving processed binary data, the processed binary data including a binary code word and an indication of whether bits of the binary code word are inverted, the binary code word including a first portion and a second portion; and

processing means for;

inverting each bit of only the first portion of the binary code word when the indication indicates that the bits are inverted, and

run length limited (RLL) decoding only the second portion of the binary code word.

11. The decoder of claim 10, wherein the indication comprises a binary digit having a first value when the bits of the binary code word are inverted and having a second value otherwise.

12. The decoder of claim 10, further comprising means for performing at least one of error correction decoding and reverse precoding of the binary code word.