Non-volatile memory device manufacturing process testing systems and methods thereof

• US 7,802,155 B2
• Filed: 03/04/2008
• Issued: 09/21/2010
• Est. Priority Date: 01/06/2000
• Status: Expired due to Fees

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Hiew, Siew Sin, Shen, Ming-Shiang, Lee, Charles C., Ma, Abraham Chih-Kang, Yu, I-Kang
• Primary Examiner(s): Gaffin; Jeffrey A
• Assistant Examiner(s): NGUYEN, STEVE N
• Application Number:
  US12/042,316
• Publication Number:
  US 20080201622A1
• Time in Patent Office: 931 Days
• Field of Search: None
• US Class Current: 714/718
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.

Claims

1. A method of testing a plurality of non-volatile memory (NVM) modules comprising:

conducting an initial open and short test on each of the plurality of NVM modules;

dividing the plurality of NVM modules into first and second groups, the first group contains said each of the plurality of NVM modules fails in the initial open and short test, while the second group contains said each of the plurality of NVM modules passes the initial open and short test;

conducting a temperature and voltage test on each of the second group of the NVM modules;

dividing the second group into third and fourth groups, the third group contains said each of the second group that fails the temperature and voltage test and the fourth group contains said each of the second group that passes the temperature and voltage test;

conducting a function test on each of the fourth group of the NVM modules;

dividing the fourth group into fifth and sixth groups, the fifth group includes said each of the fourth group that fails the function test and the sixth group includes said each of the fourth group that passes the function test; and

sending all of the first, third and fifth group of the NVM modules to a rework unit for fixing failure-causing defect;

wherein the open and short test is configured to detect any open and short condition, and the temperature and voltage test is configured to determine whether operating temperature and voltage tolerance are met;

wherein said conducting the function test further comprises;

coupling at least one of the sixth group of the NVM modules to a plurality of NVM test modules mounted on a main testing platform, each of the at least one of the sixth group of the NVM modules corresponds to a respective one of the plurality of NVM test modules;

initializing each of the at least one of the sixth group of the NVM modules by the main testing platform; and

verifying data written to said each the at least one of the sixth group with a test vector created by the respective one of the NVM test modules;

wherein said each of the at least one of the sixth group of the NVM modules further comprises;

receiving a command from the host at said each of the at least one of the sixth group of the NVM modules to check manufacturer'"'"'s identification (ID) of NVM;

sending the ID to the main testing platform to obtain a set of specific characteristics corresponding to the ID in a database stored thereon;

receiving a boot code and a run code to perform a self test; and

when the self test passes, formatting said each of the at least one of the sixth group of the NVM modules and loading an operating system image thereto.

2. The method of claim 1 further comprising:

conducting final quality assurance test under an operating temperature range between −

40 and 85 degrees Celsius on each of the sixth group of the NVMs to determine whether said each of the sixth group of the NVMs operates without error.

3. The method of claim 1, receiving the boot code and the run code comprises receiving the NVM timing parameters at NVM interface in said each of the at least one of the sixth group of the NVM modules.

4. The method of claim 3, wherein the run code is customized by the host with the specific characteristics corresponding to the ID of said each of the at least one of the sixth group of the NVM modules.

5. The method of claim 1, further comprises determining a bad block list to ensure number of bad blocks is within an acceptable threshold for said each of the at least one of the sixth group of the NVM modules.

6. The method of claim 1, wherein the test vector comprises a known sequence of data bits.

7. The method of claim 1, wherein the test vector comprises a repeatable random sequence of data bits that is produced by a pseudo random number generator.

8. The method of claim 1, wherein the test vector is written to a portion of NVM in a predefined direction according to a special function test command.

9. The method of claim 8, the predefined direction includes forward and backward.