Design automation using spine routing
First Claim
1. A method comprising:
- providing N pins to couple together using a net;
by a computer, finding a rectangular route region, comprising the N pins, having a length greater than a width, wherein the length is in a first direction and the width is a second direction, orthogonal to the first direction, the rectangular route area is bounded by a first, second, third, and fourth side of the rectangular route area, the third side is opposite of the first side, the fourth side is opposite of the second side, the first side is longer than the second side, the first and third sides extend in the first direction, the second and fourth sides extend in the second direction;
in the rectangular route region, placing a first spine interconnect extending in the first direction at a position in the second direction from the first or third side of the rectangular route area based on a quotient of a sum of the positions of the N pins in the second direction and N; and
in the rectangular route region, routing N stitching interconnects in the second direction to couple each of the N pins to the first spine interconnect.
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Abstract
A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.
106 Citations
27 Claims
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1. A method comprising:
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providing N pins to couple together using a net; by a computer, finding a rectangular route region, comprising the N pins, having a length greater than a width, wherein the length is in a first direction and the width is a second direction, orthogonal to the first direction, the rectangular route area is bounded by a first, second, third, and fourth side of the rectangular route area, the third side is opposite of the first side, the fourth side is opposite of the second side, the first side is longer than the second side, the first and third sides extend in the first direction, the second and fourth sides extend in the second direction; in the rectangular route region, placing a first spine interconnect extending in the first direction at a position in the second direction from the first or third side of the rectangular route area based on a quotient of a sum of the positions of the N pins in the second direction and N; and in the rectangular route region, routing N stitching interconnects in the second direction to couple each of the N pins to the first spine interconnect. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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providing N pins to couple together using a first net by a computer, finding a rectangular route region, comprising the N pins, having a length greater than a width, wherein the length is in a first direction and the width is a second direction, orthogonal to the first direction; in the rectangular route region, placing a first spine interconnect extending in the first direction at a position in the second direction based on a quotient of a sum of the positions of the N pins in the second direction and N; routing N stitching interconnects in the second direction to couple each of the N pins to the first spine interconnect, wherein the first spine interconnect and N stitching interconnects forms a first interconnect track; providing M pins to couple together using a second net; in the rectangular route region, placing a second spine interconnect extending in the first direction at a position in the second direction; routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect, wherein the second spine interconnect and M stitching interconnects forms a second interconnect track; placing a first shield interconnect adjacent to the first spine interconnect on a first side; and placing a second shield interconnect adjacent to the first spine interconnect, between the first spine interconnect and the second spine interconnect.
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9. A method comprising:
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providing N pins to couple together using a first net by a computer, finding a rectangular route region, comprising the N pins, having a length greater than a width, wherein the length is in a first direction and the width is a second direction, orthogonal to the first direction; in the rectangular route region, placing a first spine interconnect extending in the first direction at a position in the second direction based on a quotient of a sum of the positions of the N pins in the second direction and N; routing N stitching interconnects in the second direction to couple each of the N pins to the first spine interconnect, wherein the first spine interconnect and N stitching interconnects forms a first interconnect track; providing M pins to couple together using a second net; in the rectangular route region, placing a second spine interconnect extending in the first direction at a position in the second direction; routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect, wherein the second spine interconnect and M stitching interconnects forms a second interconnect track; placing a first shield interconnect adjacent to the first spine interconnect on a first side; and placing a second shield interconnect adjacent to the second spine interconnect, wherein the first and second spine interconnects are between the first and second shield interconnects.
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10. A method for routing at least one interconnect of an integrated circuit comprising:
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identifying N pins to couple; by a computer, calculating a rectangular route area to comprise the positions in a first direction of the N pins, wherein the rectangular route area is bounded by a first, second, third, and fourth side of the rectangular route area, the third side is opposite of the first side, the fourth side is opposite of the second side, the first side is longer than the second side, the first and third sides extend in the first direction, and the second and fourth sides extend in a second direction; determining if at least one forbidden area is located within the route area; routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction, wherein the spine interconnect is within the rectangular route area; and routing N stitching interconnects in the second direction to couple each of the N pins to the spine interconnect, wherein each of the N stitching interconnects is shorter than spine interconnect, each of the N stitching interconnects is within the rectangular route area, the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction, and the first direction is orthogonal to the second direction. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method comprising:
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providing a rectangular gridless routing area having a length dimension L greater than a width dimension W, wherein the routing area comprises a plurality of first pins to be coupled together using a first interconnect, a plurality of second pins to be coupled together using a second interconnect; by a computer, within the gridless routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length L of the routing area and a uniform first width between the straight edges; within the gridless routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length L of the routing area and the uniform first width between the straight edges; generating a first plurality of stitch polygons, extending perpendicularly to the first spine polygon, to couple each of the first pins to the first polygon; and generating a second plurality of stitch polygons, extending perpendicularly to the first spine polygon, to couple each of the second pins to the second polygon. - View Dependent Claims (19, 20, 21, 22, 23, 25, 26, 27)
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24. The method of 18 wherein the design constraint comprises at least one of spacing constraint, crosstalk constraint, capacitance constraint, or timing constraint.
Specification