Method of manufacturing a thin film transistor substrate

• US 7,803,673 B2
• Filed: 10/12/2007
• Issued: 09/28/2010
• Est. Priority Date: 10/12/2006
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Duck-Jung, Song, Dae-Ho, Kim, Kyung-Seop, Lee, Yong-Eui
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Abdelaziez; Yasser A
• Application Number:
  US11/871,457
• Publication Number:
  US 20080090342A1
• Time in Patent Office: 1,082 Days
• Field of Search: 345/87
• US Class Current: 438/158
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate

Abstract

A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a gate insulating film and an active layer on a substrate, forming a data metal layer including a first, second, and third metal layers on the active layer, forming a first photoresist pattern on the data metal layer, dry-etching the third metal layer by using the first photoresist pattern, simultaneously dry-etching the second and first metal layers by using the first photoresist pattern, dry-etching the active layer by using the first photoresist pattern, etching the first photoresist pattern to form a second photoresist pattern by which the channel region is removed and forming a source electrode and a drain electrode by dry-etching the channel region of the data metal layer by using the second photoresist pattern.

Claims

1. A method of manufacturing a thin film transistor substrate, the method comprising:

sequentially forming a gate insulating film and an active layer on a substrate, the substrate having a gate wire including a gate line and a gate electrode connected to the gate line formed thereon;

forming a data metal layer on the active layer, the data metal layer including a first metal layer, a second metal layer and a third metal layer disposed, in sequence;

forming a first photoresist pattern on the data metal layer, the first photoresist pattern having a thinner thickness at a channel region than at an adjacent region;

dry-etching the third metal layer by using the first photoresist pattern;

simultaneously dry-etching the second metal layer and the first metal layer by using the first photoresist pattern to form a data line;

dry-etching the active layer by using the first photoresist pattern;

removing a portion of the first photoresist pattern to form a second photoresist pattern by which the channel region is removed; and

forming a source electrode connected to the data line and a drain electrode spaced apart from the source electrode by dry-etching the channel region of the data metal layer by using the second photoresist pattern.

2. The method of claim 1, wherein the first metal layer comprises molybdenum, the second metal layer includes aluminum and the third metal layer includes molybdenum.

3. The method of claim 2, wherein boron trichloride (BCl₃) and chlorine gas (Cl₂) are used for simultaneously etching the second metal layer and the first metal layer by using the first photoresist pattern.

4. The method of claim 3, wherein boron trichloride (BCl₃) and chlorine gas (Cl₂) are mixed in a ratio from about 1:

1 to about 1;

5.

5. The method of claim 1, wherein dry-etching the channel region of the data metal layer by using the second photoresist pattern comprises:

dry-etching the third metal layer by using the second photoresist pattern; and

simultaneously dry-etching the second metal layer and the first metal layer by using the second photoresist pattern.

6. The method of claim 1, wherein the active layer comprises a channel layer having amorphous silicon and an ohmic contact layer having amorphous silicon in which ions are doped, and

the method further comprising forming a thin film transistor by removing the ohmic contact layer within the channel region by using the second photoresist pattern after forming the source electrode and the drain electrode.

7. The method of claim 6, further comprising:

forming a protective film on the substrate having the thin film transistor formed thereon; and

forming a pixel electrode on the protective film, the pixel electrode electrically connected to the drain electrode.

8. A method of manufacturing a thin film transistor substrate, the method comprising:

sequentially forming a gate insulating film and an active layer on a substrate, the substrate having a gate wire including a gate line and a gate electrode connected to the gate line formed thereon;

forming a data metal layer on the active layer, the data metal layer including a first metal layer, a second metal layer and a third metal layer disposed, in sequence;

forming a photoresist pattern on the data metal layer having a thinner thickness at a channel region than at an adjacent region;

dry-etching the third metal layer by using the photoresist pattern;

dry-etching the second metal layer by using the photoresist pattern;

simultaneously dry-etching the first metal layer and the active layer by using the photoresist pattern to form a data line; and

forming a source electrode connected to the data line and a drain electrode spaced apart from the source electrode by dry-etching the channel region of the data metal layer by using the photoresist pattern.

9. The method of claim 8, wherein the first metal layer comprises molybdenum, the second metal layer comprises aluminum, and the third metal layer comprises molybdenum.

10. The method of claim 9, wherein fluorine (F) series gas and chlorine gas (Cl₂) are used for simultaneously etching the first metal layer and the active layer by using the photoresist pattern.

11. The method of claim 10, wherein the fluorine (F) series gas comprises sulfur hexafluoride (SF₆) gas.

12. The method of claim 11, wherein sulfur hexafluoride (SF₆) and chlorine gas (Cl₂) are mixed in a ratio from about 1:

5 to about 1;

7.

13. The method of claim 8, wherein the third metal layer is simultaneously etched in an area corresponding to the channel region in a process of simultaneously dry-etching the first metal layer and the active layer by using the photoresist pattern.

14. The method of claim 8, wherein the active layer comprises a channel layer having amorphous silicon and an ohmic contact layer having amorphous silicon in which ions are doped, and

the method further comprising forming a thin film transistor by removing the ohmic contact layer within the channel region by using the photoresist pattern after forming the source electrode and the drain electrode.

15. The method of claim 14, further comprising:

forming a protective film on the substrate having the thin film transistor; and

forming a pixel electrode on the protective film, the pixel electrode electrically connected to the drain electrode.

16. A method of manufacturing a thin film transistor substrate, the method comprising:

sequentially forming a gate insulating film and an active layer on a substrate, the substrate having a gate wire including a gate line and a gate electrode connected to the gate line formed thereon;

forming a data metal layer on the active layer, the data metal layer including a first metal layer, a second metal layer and a third metal layer disposed in sequence;

forming a photoresist pattern on the data metal layer having a thinner thickness at a channel region than at an adjacent region;

dry-etching the third metal layer by using the photoresist pattern;

dry-etching the second metal layer by using the photoresist pattern;

dry-etching the first metal layer by using the photoresist pattern; and

,

dry-etching the active layer by using the photoresist pattern;

wherein at least two dry-etching processes dry-etching the third metal layer, the second metal layer, the first metal layer, and the active layer by using the photoresist pattern are performed simultaneously.

17. The method of claim 16, wherein the method does not include a wet-etching process.

18. The method of claim 16, wherein the first metal layer includes molybdenum, the second metal layer includes aluminum, and the third metal layer includes molybdenum.

19. The method of claim 16, wherein dry-etching the second metal layer and dry-etching the first metal layer are performed simultaneously.

20. The method of claim 16, wherein dry-etching the first metal layer and dry-etching the active layer are performed simultaneously.