Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory
First Claim
1. A device structure for a non-volatile random access memory formed on an insulating layer, the device structure comprising:
- a semiconductor body in direct contact with the insulating layer, the semiconductor body including a source, a drain, and a channel between the source and the drain;
a control gate electrode;
a floating gate electrode in direct contact with the insulating layer, the floating gate electrode juxtaposed with the channel of the semiconductor body, and the floating gate electrode disposed between the control gate electrode and the insulating layer;
a first dielectric layer disposed between the channel of the semiconductor body and the floating gate electrode; and
a second dielectric layer disposed between the control gate electrode and the floating gate electrode, the second dielectric layer in contact with the semiconductor body.
3 Assignments
0 Petitions
Accused Products
Abstract
Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.
-
Citations
15 Claims
-
1. A device structure for a non-volatile random access memory formed on an insulating layer, the device structure comprising:
-
a semiconductor body in direct contact with the insulating layer, the semiconductor body including a source, a drain, and a channel between the source and the drain; a control gate electrode; a floating gate electrode in direct contact with the insulating layer, the floating gate electrode juxtaposed with the channel of the semiconductor body, and the floating gate electrode disposed between the control gate electrode and the insulating layer; a first dielectric layer disposed between the channel of the semiconductor body and the floating gate electrode; and a second dielectric layer disposed between the control gate electrode and the floating gate electrode, the second dielectric layer in contact with the semiconductor body. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A design structure embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
-
a semiconductor body in direct contact with an insulating layer, the semiconductor body including a source, a drain, and a channel between the source and the drain; a control gate electrode; a floating gate electrode in direct contact with the insulating layer, the floating gate electrode juxtaposed with the channel of the semiconductor body, and the floating gate electrode disposed between the control gate electrode and the insulating layer; a first dielectric layer disposed between the channel of the semiconductor body and the floating gate electrode; and a second dielectric layer disposed between the control gate electrode and the floating gate electrode, the second dielectric layer in contact with the semiconductor body. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
-
Specification