Opto-thermal mask including aligned thermal dissipative layer, reflective layer and transparent capping layer

• US 7,804,148 B2
• Filed: 02/16/2006
• Issued: 09/28/2010
• Est. Priority Date: 02/16/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L., Sung, Chun-Yung, Mandelman, Jack A., Narayan, Chandrasekhar
• Primary Examiner(s): Cao; Phat X
• Assistant Examiner(s): VIEIRA, DIANA C
• Application Number:
  US11/355,799
• Publication Number:
  US 20070187670A1
• Time in Patent Office: 1,685 Days
• Field of Search: 257/1, 257/24, 257/192, 257/410, 257/411, 257/435, 257/184, 257/290, 257/433, 257/E29.324, 257/98, 257/695, 257/659, 257/471, 257/469, 257/E21.035, 257/E21.036, 257/432, 257/48, 257/467, 257/431, 257/629, 257/E31.11, 257/E31.127, 257/E31.131, 438/550, 438/660, 438/661, 438/662, 438/530, 438/540, 438/795, 438/308, 438/902, 438/50, 438/52, 438/582, 438/142, 438/54, 438/55, 438/69, 438/72, 438/64, 438/71
• US Class Current: 257/435
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.

Claims

1. A structure comprising:

a microelectronic structure having a substrate and a plurality of layers, each layer having an upper and a lower surface and four sidewall surfaces, each said upper and lower surface defining a flat area,

a thermal dissipative layer having a thickness of from about 500 to 1500 Å

, selected from the group consisting of a thermally dissipative diamond-like carbon material, titanium, tungsten, tantalum, and nitrides and silicides and alloys thereof, the lower surface area of said thermal dissipative layer located over and being in spatially continuous contact with all or a portion of an upper surface area of said substrate, wherein said substrate is selected from the group consisting of a bulk semiconductor substrate, a semiconductor-on-insulator substrate, and a hybrid semiconductor substrate comprising at least one bulk semiconductor region and at least one semiconductor-on-insulator region;

a reflective layer having a thickness of from about 500 to 1000 Å

, and being a non-refractory metal material selected from the group consisting of aluminum metal material and copper metal material, the lower surface area of said reflective layer being located over and in spatially continuous contact with the upper surface area of said thermal dissipative layer and said reflective layer is located upon the entirety of said area of said thermal dissipative layer; and

a dielectric transparent capping layer selected from the group consisting of indium-tin oxide, silicon oxide, silicon nitride and silicon oxynitride having a thickness of from about 10 to 100 Å

, said dielectric transparent capping layer located directly upon said reflective layer, such that the lower surface area of said dielectric transparent capping layer is located over and in spatially continuous spatial contact with the upper surface area of said reflective layer wherein a given sidewall of each of said thermal dissipative layer, said reflective layer and said transparent capping layer is aligned with respect to one another.

2. The structure of claim 1 wherein the capping layer has a thickness from about 10 to about 100 angstroms.

3. The structure of claim 1 wherein the substrate comprises a bulk semiconductor substrate.

4. The structure of claim 1 wherein the substrate comprises a semiconductor-on-insulator substrate.

5. The structure of claim 1 wherein the substrate comprises a hybrid semiconductor substrate comprising at least one bulk semiconductor region and at least one semiconductor-on-insulator region.

6. The structure of claim 1 wherein:

the thermal dissipative layer comprises a refractory metal; and

the reflective layer comprises a non-refractory metal.

7. The structure of claim 1 wherein:

the thermal dissipative layer comprises a thermal dissipative diamond like carbon material; and

the reflective layer is a non-refractory metal material selected from the consisting of aluminum metal material and copper metal material.

8. A structure comprising:

a microelectronic structure having a substrate and plurality of layers, each layer having an upper and a lower surface and four sidewall surfaces, each said upper and lower surface defining a flat spatial area,

a lower surface of a thermal dissipative layer located over an in spatially continuous contact with a portion of the upper surface of said substrate;

the lower surface of a reflective layer located upon the entirety of and in spatially continuous contact with the upper surface of said thermal dissipative layer;

a dielectric transparent capping layer having a lower surface located directly upon and in spatially continuous contact with the reflective layer, wherein a given sidewall of each of said thermal dissipative layer, said reflective layer and said transparent capping layer is aligned with respect to one another to provide a stack located over a first portion of said upper surface of said substrate;

and an optical interference layer having a lower incident radiation reflectance than the reflective layer located laterally with respect to the stack over a second portion of said upper surface of said substrate that does not include said first portion of the substrate.