Lateral trench gate FET with direct source-drain current path

• US 7,804,150 B2
• Filed: 06/29/2006
• Issued: 09/28/2010
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Jeon, Chang-ki, Dolny, Gary
• Primary Examiner(s): Lee; Eugene
• Assistant Examiner(s): Gumedzoe; Peniel M
• Application Number:
  US11/479,149
• Publication Number:
  US 20080001198A1
• Time in Patent Office: 1,552 Days
• Field of Search: 257/110, 257/120, 257/492, 257/493, 257/E29.027, 257/E29.066, 257/E29.256, 257/E29.257, 257/E29.26, 257/E21.417, 257/E21.418, 257/E21.435
• US Class Current: 257/492
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor includes a trench gate extending into a semiconductor region. The trench gate has a front wall facing a drain region and a side wall perpendicular to the front wall. A channel region extends along the side wall of the trench gate, and a drift region extends at least between the drain region and the trench gate. The drift region includes a stack of alternating conductivity type silicon layers.

Claims

1. A field effect transistor (FET) comprising:

a trench gate extending into a semiconductor region, the trench gate having a front wall facing a drain region of a first conductivity type and a side wall perpendicular to the front wall;

a body region of a second conductivity type abutting the side wall of the trench gate;

a source region of the first conductivity type abutting the side wall of the trench gate and extending in the body region so as to form a channel region in the body region along the side wall of the trench gate, the source region extending in a middle portion of the body region such that when the FET is in an on state, portions of a current that flows through the channel region flow in opposite directions; and

a drift region extending at least between the drain region and the trench gate, the drift region comprising a stack of alternating conductivity type silicon layers.

2. The FET of claim 1 wherein when the FET is in the on state, the current flows laterally through those silicon layers of the stack having the first conductivity type.

3. The FET of claim 1 wherein the channel region extends in the body region between an outer perimeter of the source region and an outer perimeter of the body region.

4. The FET of claim 3 wherein the source region and the drain region are electrically contacted by separate interconnect layers formed on a top surface of the FET.

5. The FET of claim 3 further comprising a substrate of the second conductivity type, the stack of alternating conductivity type silicon layers extending over the substrate, wherein the trench gate extends into the stack of alternating conductivity type silicon layers and terminates at a depth within a lower half of a distance between a bottom surface of the body region and a top surface of the substrate.

6. The FET of claim 3 further comprising a heavy body region adjacent to the source region.

7. The FET of claim 6 further comprising a substrate of the second conductivity type, the stack of alternating conductivity type silicon layers extending over the substrate, wherein the heavy body region vertically extends through the stack of alternating conductivity type silicon layers and terminates within the substrate.

8. The FET of claim 6 wherein the heavy body region vertically extends through the stack of alternating conductivity type silicon layers and electrically shorts those silicon layers of the stack having the second conductivity type.

9. The FET of claim 1 wherein the trench gate comprises:

a dielectric layer lining the front and side walls of the trench gate; and

a gate electrode at least partially filling the trench gate.

10. The FET of claim 9 wherein the dielectric layer is thicker along the bottom of the trench gate than along its walls.

11. The FET of claim 9 wherein the dielectric layer is thicker along the bottom and the front wall of the trench gate than along its side wall.

12. The FET of claim 1 wherein those silicon layers of the stack having a second conductivity type are laterally spaced from the side wall of the trench gate so as not to extend beneath the channel region.

13. The FET of claim 1 wherein those silicon layers of the stack having a second conductivity type do not extend underneath the channel region.

14. The FET of claim 1 wherein the drain region vertically extends through the stack of alternating conductivity type silicon layers and electrically shorts those silicon layers of the stack having the first conductivity type.

15. The FET of claim 1 further comprising a substrate of the second conductivity type, the stack of alternating conductivity type silicon layers extending over the substrate, wherein the drain region vertically extends through the stack of alternating conductivity type silicon layers and terminates within the substrate.

16. A lateral field effect transistor (FET) comprising:

a plurality of trench gates extending into a semiconductor region, the plurality of trench gates being arranged along columns, each trench gate having two active sidewalls and two non-active sidewalls, the two non-active sidewalls being perpendicular to the two active sidewalls;

a plurality of drain regions of a first conductivity type, each drain region being located between every two adjacent columns of trench gates such that each non-active sidewall of each trench gate faces the adjacent drain region, each drain region being laterally spaced from the adjacent columns of trench gates;

a channel region extending along each active sidewall of the plurality of trench gates such that when the lateral FET is in an on state, portions of a current that flows through the channel region flow in opposite directions; and

a drift region extending between the drain regions and their adjacent columns of trench gates and between adjacent trench gates, the drift region comprising a stack of alternating conductivity type silicon layers.

17. The lateral FET of claim 16 wherein when the lateral FET is in the on state, the current flows laterally through those silicon layers of the stack having the first conductivity type.

18. The lateral FET of claim 16 further comprising:

a body region of the second conductivity type located adjacent each active sidewall of each trench gate; and

a source region of the first conductivity type in each body region, wherein each channel region extends in a corresponding body region between an outer perimeter of the source region and an outer perimeter of the body region.

19. The lateral FET of claim 18 wherein the source regions and the drain regions are electrically contacted by separate interconnect layers formed on a top surface of the lateral FET.

20. The lateral FET of claim 18 further comprising a heavy body region between every two adjacent source regions.

21. The lateral FET of claim 20 further comprising a substrate of the second conductivity type, the stack of alternating conductivity type silicon layers extending over the substrate, wherein each heavy body region vertically extends through the stack of alternating conductivity type silicon layers and terminates within the substrate.

22. The lateral FET of claim 20 wherein each heavy body region vertically extends through the stack of alternating conductivity type silicon layers and electrically shorts those silicon layers of the stack having the second conductivity type.

23. The lateral FET of claim 16 wherein each trench gate comprises:

a dielectric layer lining the active sidewalls, the non-active sidewalls and bottom of the trench; and

a gate electrode at least partially filling the trench gate.

24. The lateral FET of claim 23 wherein the dielectric layer is thicker along the bottom of the trench gate than along its active and non-active sidewalls.

25. The lateral FET of claim 23 wherein the dielectric layer is thicker along the bottom and the non-active sidewalls of the trench gate than along its active sidewalls.

26. The lateral FET of claim 16 wherein those silicon layers of the stack having a second conductivity type are laterally spaced from each active sidewall so as not to extend beneath the channel region.

27. The lateral FET of claim 16 wherein those silicon layers of the stack having a second conductivity type do not extend underneath each channel region.

28. The lateral FET of claim 16 wherein each drain region vertically extends through the stack of alternating conductivity type silicon layers and electrically shorts those silicon layers of the stack having the first conductivity type.

29. The lateral FET of claim 16 further comprising a substrate of the second conductivity type, the stack of alternating conductivity type silicon layers extending over the substrate, wherein each drain region vertically extends through the stack of alternating conductivity type silicon layers and terminates within the substrate.