Voltage level shifter

• US 7,804,326 B1
• Filed: 11/30/2009
• Issued: 09/28/2010
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Elite Semiconductor Memory Technology Inc.
• Original Assignee: Elite Semiconductor Memory Technology Inc.
• Inventors: Chen, Chung-Zen
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/627,107
• Time in Patent Office: 302 Days
• Field of Search: 326/62, 326/63, 326/68, 326 80- 83
• US Class Current: 326/68
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence

Abstract

A voltage level shifter comprises a voltage adjustment circuit, an inverter, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second NMOS transistor. The voltage adjustment circuit is configured for receiving a first voltage and a second voltage and for generating an adjustment voltage. When the first voltage is higher than the second voltage, the adjustment voltage is substantially equal to the first voltage, and when the first voltage is lower than the second voltage, the adjustment voltage is substantially equal to the second voltage.

Claims

1. A voltage level shifter, comprising:

a voltage adjustment circuit configured for receiving a first voltage and a second voltage and for generating an adjustment voltage;

an inverter configured for receiving an input signal and for operating at the first voltage;

a first NMOS transistor having a gate connected to an output terminal of the inverter, a drain connected to an output signal, and a source connected to a reference voltage;

a second NMOS transistor having a gate connected to the first voltage and a source connected to the output terminal of the inverter;

a first PMOS transistor having a gate connected to the output signal, a drain connected to a drain of the second NMOS transistor, and a source connected to the adjustment voltage; and

a second PMOS transistor having a gate connected to the drain of the second NMOS transistor, a drain connected to the output signal, and a source connected to the adjustment voltage;

wherein when the first voltage is higher than the second voltage, the adjustment voltage is substantially equal to the first voltage, and when the first voltage is lower than the second voltage, the adjustment voltage is substantially equal to the second voltage.

2. The voltage level shifter of claim 1, wherein the voltage adjustment circuit comprises:

a voltage generator configured for receiving the first voltage and for generating a first output signal according to an enable signal;

a comparing circuit configured for comparing the first output signal with the second voltage and for generating the enable signal and an inverted enable signal; and

a selector configured for receiving the first output signal and the second voltage and for generating the adjustment voltage according to the inverted enable signal.

3. The voltage level shifter of claim 2, wherein the voltage generator comprises:

a voltage regulator configured for receiving the enable signal; and

a first NMOS transistor having a gate connected to an output terminal of the voltage regulator, a drain connected to the first voltage, and a source configured for generating the first output signal.

4. The voltage level shifter of claim 3, wherein the voltage generator further comprises a second NMOS transistor, the second NMOS transistor has a gate connected to the inverted enable signal, a drain connected to the gate of the first NMOS transistor, and a source connected to the reference voltage.

5. The voltage level shifter of claim 3, wherein the voltage regulator is a step-up voltage converter or a charge pump.

6. The voltage level shifter of claim 3, wherein the voltage regulator is non-activated when the second voltage is higher than the first output signal.

7. The voltage level shifter of claim 2, wherein the comparing circuit is non-activated when the second voltage is higher than the first output signal.

8. The voltage level shifter of claim 2, wherein the comparing circuit further comprises a pull-up unit configured for receiving a power-up signal and for generating the enable signal according to the power-up signal.

9. The voltage level shifter of claim 8, wherein the pull-up unit is a PMOS transistor.

10. A voltage level shifter, comprising:

a voltage adjustment circuit configured for receiving a first voltage and a second voltage and for generating an adjustment voltage;

an inverter configured for receiving an input signal and for operating at the adjustment voltage;

a first PMOS transistor having a gate connected to an output terminal of the inverter, a drain connected to the output signal, and a source connected to the first voltage;

a second PMOS transistor having a gate connected to a reference voltage and a source connected to the output terminal of the inverter;

a first NMOS transistor having a gate connected to the output signal, a drain connected to a drain of the second PMOS transistor, and a source connected to the reference voltage; and

a second NMOS transistor having a gate connected to the drain of the second PMOS transistor, a drain connected to the output signal, and a source connected to the reference voltage;

wherein when the first voltage is higher than the second voltage, the adjustment voltage is substantially equal to the first voltage, and when the first voltage is lower than the second voltage, the adjustment voltage is substantially equal to the second voltage.

11. The voltage level shifter of claim 10, wherein the voltage adjustment circuit comprises:

a voltage generator configured for receiving the first voltage and for generating a first output signal according to an enable signal;

a comparing circuit configured for comparing the first output signal with the second voltage and for generating the enable signal and an inverted enable signal; and

a selector configured for receiving the first output signal and the second voltage and for generating the adjustment voltage according to the inverted enable signal.

12. The voltage level shifter of claim 11, wherein the voltage generator comprises:

a voltage regulator configured for receiving the enable signal; and

a first NMOS transistor having a gate connected to an output terminal of the voltage generator, a drain connected to the first voltage and a source, configured for generating the first output signal.

13. The voltage level shifter of claim 12, wherein the voltage generator further comprises a second NMOS transistor, the second NMOS transistor has a gate connected to the inverted enable signal, a drain connected to the gate of the first NMOS transistor, and a source connected to the reference voltage.

14. The voltage level shifter of claim 12, wherein the voltage regulator is a step-up voltage converter or a charge pump.

15. The voltage level shifter of claim 12, wherein the voltage regulator is non-activated when the second voltage is higher than the first output signal.

16. The voltage level shifter of claim 11, wherein the comparing circuit is non-activated when the second voltage is higher than the first output signal.

17. The voltage level shifter of claim 11, wherein the comparing circuit further comprises a pull-up unit configured for receiving a power-up signal and for generating the enable signal according to the power-up signal.

18. The voltage level shifter of claim 17, wherein the pull-up unit is a PMOS transistor.