Partial block erase architecture for flash memory

• US 7,804,718 B2
• Filed: 07/18/2007
• Issued: 09/28/2010
• Est. Priority Date: 03/07/2007
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US11/779,685
• Publication Number:
  US 20080219053A1
• Time in Patent Office: 1,168 Days
• Field of Search: 365/185.02, 365/185.03, 365/185.11 X, 365/185.17, 365/185.27, 365/185.29 O, 365/185.33 X, 365/185.11, 365/185.29, 365/185.33
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations.

Claims

1. A flash memory device comprising:

a memory array having at least one block of NAND flash memory cell strings arranged in columns where each of the NAND flash memory cell strings includes flash memory cells, the at least one block having pages programmable in a predetermined direction from a first wordline to a last wordline, and the at least one block also having a sequential set of first wordlines dynamically configurable by a starting address; and

,

row circuitry for driving the first wordlines to a first voltage when the substrate is biased to an erase voltage for concurrently erasing the flash memory cells connected to the first wordlines, the row decoders driving second wordlines to a second voltage for inhibiting erasure of the flash memory cells coupled to the second wordlines, the second wordlines including a first unselected wordline up to a last unselected wordline, and the first wordlines including a first selected wordline addressed by the starting address adjacent to the last unselected wordline, up to a last selected wordline.

2. The flash memory device of claim 1, wherein the flash memory cells connected to the sequential set of first wordlines are multi-bit-cells (MBC).

3. The flash memory device of claim 1, wherein the sequential set of first wordlines is a first sequential set of first wordlines, and the at least one block includes a second sequential set of third wordlines, the second sequential set of third wordlines being connected to flash memory cells which are concurrently eraseable, the first sequential set of first wordlines and the second sequential set of third wordlines being non-adjacent to each other.

4. The flash memory device of claim 1, wherein the NAND flash memory cell strings of the at least one block are coupled to a common source line, and the flash memory device further includes a source line voltage control circuit for setting a voltage of the common source line between a third voltage and a fourth voltage during an erase verify operation.

5. The flash memory device of claim 4, wherein the fourth voltage is less than the third voltage, and the voltage of the common source line decreases as a number of first wordlines increases.

6. The flash memory device of claim 1, wherein the last selected wordline includes the last wordline.

7. The flash memory device of claim 1, wherein the flash memory cells that are connected to third wordlines between the last selected wordline and a select device store data.

8. The flash memory device of claim 7, wherein the flash memory cells that are connected to the third wordlines are repeatedly erasable and programmable.

9. The flash memory device of claim 1, wherein the flash memory cells that are connected to third wordlines between the last selected wordline and a select device are erased.

10. The flash memory device of claim 9, wherein the flash memory cells connected to the first wordlines are repeatedly erasable and programmable while the flash memory cells that are connected to the third wordlines are erased.

19. The flash memory device of claim 1, wherein the last selected wordline is addressable by an end address.

20. The flash memory device of claim 19, wherein the end address is preset as the last wordline.

21. The flash memory device of claim 19, wherein the end address addresses the last selected wordline between the first selected wordline addressed by the starting address and the last wordline.

11. A flash memory device comprising:

a memory array having at least one block of NAND flash memory cell strings arranged in columns, the at least one block having pages programmable in a predetermined direction from a first page to a last page; and

,

row circuitry for concurrently erasing a sequential set of pages dynamically configurable by a starting address, when the substrate is biased to an erase voltage.

12. The flash memory device of claim 11, wherein the sequential set of pages forms a sub-block.

13. The flash memory device of claim 12, wherein the sub-block includes the pages from the first page to a first intermediate page.

14. The flash memory device of claim 13, wherein the sub-block is a lower sub-block, and the pages from a second intermediate page adjacent to the first intermediate page to the last page form at least one upper sub-block.

15. The flash memory device of claim 12, wherein the sub-block includes the pages from a first intermediate page to the last page.

16. The flash memory device of claim 15, wherein the sub-block is an upper sub-block, and the pages from the first intermediate page to a second intermediate page adjacent to the first intermediate page form at least one lower sub-block.

17. The flash memory device of claim 16, wherein the at least one lower sub-block is inhibited from being erased while the upper sub-block is being erased.

18. The flash memory device of claim 12, wherein the sub-block includes the pages from a first intermediate page to a second intermediate page.

22. The flash memory device of claim 11, wherein a first selected page of the sequential set of pages is addressable by the starting address.

23. The flash memory device of claim 22, wherein a last selected page of the sequential set of pages is addressable by an end address.

24. The flash memory device of claim 23, wherein the end address is preset as being a last page of the at least one block.