Method and apparatus for accessing contents of memory cells

• US 7,804,730 B2
• Filed: 05/07/2007
• Issued: 09/28/2010
• Est. Priority Date: 03/15/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason, Schmit, Herman
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US11/745,442
• Publication Number:
  US 20070242529A1
• Time in Patent Office: 1,240 Days
• Field of Search: 365/189.01, 365/222
• US Class Current: 365/222
• CPC Class Codes: G11C 2207/2281 Timing of a read operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The invention relates to accessing contents of memory cells. Some embodiments include a memory structure that has a first cell, a second cell, and a sense amplifier. The first cell stores a first value. The first and second cells are connected to the sense amplifier by one or more bit lines. The sense amplifier receives the first value stored by the first cell by using the one or more bit lines and drives the received first value to the second cell through the one or more bit lines. The receiving and driving occur in a single clock cycle. In some embodiments, the second cell outputs the first value. The memory structure of some embodiments also includes a third cell connected to the sense amplifier by the one or more bit lines. The sense amplifier drives a second value to the third cell while the second cell outputs the first value. Other embodiments include a method for accessing data in a memory structure. The method receives a value stored by a first cell; and drives the received value to a second cell. The receiving and driving occur in a single time period. In some embodiments, the method also includes driving a first value to the second cell in a first time period and driving a second value to a third cell in a second time period. In these embodiments, the second cell outputs the first value during the second time period and the third cell outputs the second value during a third time period.

Claims

1. A method for accessing data in a memory structure, said method comprising:

receiving a value stored by a first cell;

driving said received value to a second cell; and

from the second cell, continuously outputting said value without requiring a read operation,

wherein said first and second cells are part of a set of cells arranged in a contiguous array of cells,

wherein a third cell is located between said first and second cells.

2. The method of claim 1, wherein said receiving and driving occur in a time period that is not greater than a clock cycle.

3. The method of claim 1, wherein said array includes a plurality of rows and columns, said first and second cells are in one column.

4. The method of claim 1, wherein said value is configuration data and the memory structure is a memory used in a configurable integrated circuit having a plurality of configurable circuits that operate based on the configuration data.

5. A memory structure comprising:

a plurality of cells arranged in rows and columns; and

first, second, and third cells arranged in a particular column,

wherein the third cell is for (i) receiving and storing data from the first cell during a first time period, (ii) receiving and storing data from the second cell during a second time period, and (iii) continuously outputting each stored data without requiring a read operation.

6. The memory structure of claim 5, wherein the data that is continuously outputted by the third cell is configuration data.

7. An integrated circuit (IC) comprising:

a plurality of configurable circuits for configurably performing a number of operations based on configuration data; and

a memory structure comprising;

a memory array comprising a plurality of cells arranged in rows and columns; and

a first cell and a second cell arranged in a particular column, the first cell for storing and outputting configuration data,

wherein the second cell is for (i) receiving said configuration data from said first cell and (ii) continuously outputting said received configuration data without requiring a read operation.

8. The IC of claim 7, wherein said second cell is on a periphery of the memory array.

9. The IC of claim 7, wherein said second cell is a buffer that continuously outputs data for the entire duration that said cell stores said data.

10. The IC of claim 7, wherein at least one of said plurality of configurable circuits is for receiving the configuration data output by the second cell.