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System and method for optimizing interconnections of memory devices in a multichip module

  • US 7,805,586 B2
  • Filed: 05/10/2006
  • Issued: 09/28/2010
  • Est. Priority Date: 08/29/2002
  • Status: Active Grant
First Claim
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1. A memory module comprising;

  • a substrate;

    a memory hub having an outer perimeter, the memory hub arranged on the substrate and operable to receive memory signals;

    a plurality of memory devices arranged on the substrate, all of the memory devices arranged on the substrate being substantially equidistant from the outer perimeter of the memory hub and coupled to the memory hub by a respective bus, all of the respective buses having substantially a same length and being substantially perpendicular to the outer perimeter of the memory hub, the length being substantially equal to a shortest distance between the memory hub and the respective memory device.

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