System and method for optimizing interconnections of memory devices in a multichip module
First Claim
1. A memory module comprising;
- a substrate;
a memory hub having an outer perimeter, the memory hub arranged on the substrate and operable to receive memory signals;
a plurality of memory devices arranged on the substrate, all of the memory devices arranged on the substrate being substantially equidistant from the outer perimeter of the memory hub and coupled to the memory hub by a respective bus, all of the respective buses having substantially a same length and being substantially perpendicular to the outer perimeter of the memory hub, the length being substantially equal to a shortest distance between the memory hub and the respective memory device.
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Abstract
An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.
364 Citations
30 Claims
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1. A memory module comprising;
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a substrate; a memory hub having an outer perimeter, the memory hub arranged on the substrate and operable to receive memory signals; a plurality of memory devices arranged on the substrate, all of the memory devices arranged on the substrate being substantially equidistant from the outer perimeter of the memory hub and coupled to the memory hub by a respective bus, all of the respective buses having substantially a same length and being substantially perpendicular to the outer perimeter of the memory hub, the length being substantially equal to a shortest distance between the memory hub and the respective memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A computer system, comprising:
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a processor; a controller electrically coupled to the processor, the controller being operable to receive and transmit memory signals on a memory link; and a memory module comprising; a substrate; a memory hub having an outer perimeter, the memory hub arranged on the substrate and operable to receive memory signals from a memory link port and apply memory signals to the memory link port; and a plurality of memory devices arranged on the substrate, all of the memory devices on the substrate being substantially equidistant from the outer perimeter of the memory hub and coupled to the memory hub by a respective bus, all of the respective buses having substantially a same length and being substantially perpendicular to the outer perimeter of the memory hub, the length being substantially equal to a shortest distance between the memory hub and the respective memory device. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification