Method and apparatus for selectively compacting test responses
First Claim
1. An apparatus used in testing of an integrated circuit, comprising:
- a compactor formed from a feedback-free network of XOR or XNOR gates, the compactor having compactor inputs and compactor outputs, the number of compactor outputs being less than the number of compactor inputs, the compactor being configured to compress test responses from a circuit under test; and
a selector circuit coupled to the compactor inputs, the selector circuit comprising logic controlled by one or more control lines, the logic being configured to either allow test response values output from one or more scan chain outputs to be input to the compactor inputs or to mask the test response values output from the one or more scan chain outputs, the test response values being responsive to deterministic test patterns applied to the integrated circuit.
2 Assignments
0 Petitions
Accused Products
Abstract
A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
-
Citations
21 Claims
-
1. An apparatus used in testing of an integrated circuit, comprising:
-
a compactor formed from a feedback-free network of XOR or XNOR gates, the compactor having compactor inputs and compactor outputs, the number of compactor outputs being less than the number of compactor inputs, the compactor being configured to compress test responses from a circuit under test; and a selector circuit coupled to the compactor inputs, the selector circuit comprising logic controlled by one or more control lines, the logic being configured to either allow test response values output from one or more scan chain outputs to be input to the compactor inputs or to mask the test response values output from the one or more scan chain outputs, the test response values being responsive to deterministic test patterns applied to the integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method for selectively compacting test responses to deterministic test patterns of an integrated circuit, comprising:
-
receiving test response values output from scan chains in an integrated circuit, the test response values being responsive to deterministic test patterns applied to the integrated circuit; selectively masking one or more of the test response values from being passed to one or more spatial compactors, the one or more masked test response values including one or more unknown test response values or one or more test response values showing a fault effect; and compacting the test response values passed to the one or more spatial compactors. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
-
Specification