Method for local hot spot fixing

• US 7,805,692 B2
• Filed: 05/15/2007
• Issued: 09/28/2010
• Est. Priority Date: 05/15/2006
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jeng, Shwang-Ming
• Primary Examiner(s): Lin; Sun J
• Application Number:
  US11/748,599
• Publication Number:
  US 20070264731A1
• Time in Patent Office: 1,232 Days
• Field of Search: 716/1, 716/4, 716/5, 716/2
• US Class Current: 716/122
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Efficient and cost-effective systems and methods for detecting and correcting hot spots of semiconductor devices are disclosed. In one aspect, a method includes providing an input file having a device layout; performing a hot spot detection on the input file; and then modifying the device layout based on the hot spots detected to create an output file. In another aspect, a method includes providing an input file having a device layout; selecting a first local region of the device layout; performing a first hot spot detection on the first local region; modifying the first local region based on the hot spots detected to create a first output file; and repeating for other local regions of the device layout. In some aspects, hot spots are detected by comparing parameters of the device layout with a set of hot spot rules to determine if the device layout satisfies the hot spot rules.

Claims

1. A method comprising:

providing an input file in an electronic format in a computer readable medium, wherein the input file comprises a device layout;

fabricating a semiconductor device corresponding to the device layout of the input file;

performing a first hot spot detection, using a first hot spot detection machine, on the input file to detect a hot spot in the device layout of the input file;

performing a second hot spot detection, using a second hot spot detection machine, on the semiconductor device to detect a hot spot in the semiconductor device; and

comparing the hot spots detected by the first and second hot spot detections in order for;

modifying the device layout of the input file based on the first hot spot detection when the hot spot is detected in the device layout to create an output file if the hot spots detected by the first and second hot spot detections are consistent with respect to each other, and

calibrating the first hot spot detection to correspond to the hot spot detected by the second hot spot detection when the hot spots detected by the first and second hot spot detections are inconsistent with respect to each other.

2. The method of claim 1, wherein the performing a first hot spot detection comprises comparing at least one parameter of the device layout to at least one of a plurality of hot spot rules to determine if the at least one hot spot rule is violated.

3. The method of claim 2, wherein the plurality of hot spot rules are stored in a hot spot rules database.

4. The method of claim 3, wherein the performing a first hot spot detection is performed by a hot spot detector, the hot spot detector in communication with the hot spot rules database.

5. The method of claim 4, wherein the modifying the device layout is performed at least partially using a computer-aided system.

6. The method of claim 5, wherein the modifying the device layout is based on a set of modification guidance parameters.

7. The method of claim 6, wherein the modification guidance parameters are based upon the at least one hot spot rule that is violated.

8. The method of claim 7, wherein the input file and the output file are in a computer-aided design format.

9. The method of claim 2, wherein the calibrating comprises calibrating the plurality of hot spot rules.

10. The method of claim 9, wherein the calibrating the plurality of hot spot rules comprises comparing the first hot spot detection based on the plurality of hot spot rules to the hot spots detected by the second hot spot detection on the semiconductor device being a test wafer and modifying the hot spot rules such that the first hot spot detection and the second hot spot detection are consistent with respect to each other.

11. A method comprising:

providing an input file in an electronic format in a computer readable medium, wherein the input file comprises a device layout having a plurality of local regions;

selecting at least one local region from the plurality of local regions of the device layout until all of the plurality of local regions of the device layout have been selected;

performing first hot spot detections, using a first hot spot detection machine, on each one of the local regions based on a plurality of hot spot rules to detect hot spots in each one of the local regions of the device layout, wherein at least one of the hot spot rules corresponds to determining a pattern density of each one of the local regions exceeding a predetermined threshold;

modifying each one of the local regions of the device layout based on the first hot spot detected to create an output file;

fabricating a semiconductor device corresponding to the output file;

performing second hot spot detections, using a second hot spot detection machine, on the semiconductor devices;

tuning the first hot spot detection machine and generating a modified output file in response to the second hot spot detections; and

fabricating another semiconductor device using the modified output file.

12. The method of claim 11, wherein the performing first hot spot detections comprises comparing at least one parameter of each one of the local regions of the device layout to at least one of the plurality of hot spot rules to determine if the at least one hot spot rule is violated.

13. The method of claim 12, wherein the modifying each one of the local regions of the device layout is performed at least partially using a computer-aided system.

14. The method of claim 13, wherein the modifying each one of the local regions of the device layout is based on a set of modification guidance parameters.

15. The method of claim 14, wherein the modification guidance parameters are based upon the at least one hot spot rule that is violated.

16. The method of claim 11, wherein the pattern density represents an area occupied by interconnects within each one of the local regions divided by a total area occupied by each one of the local regions.

17. The method of claim 16, wherein the predetermined threshold is about 90%.

18. A method comprising:

providing an input file including a device layout;

fabricating a test semiconductor device corresponding to the device layout of the input file;

comparing by a first hot spot detector at least one parameter of the device layout to at least one of a plurality of hot spot rules to determine if the at least one hot spot rule is violated by the at least one parameter of the device layout;

comparing by a second hot spot detector at least one parameter of the test semiconductor device to the at least one of the plurality of hot spot rules to determine if the at least one hot spot rule is violated by the at least one parameter of the test semiconductor device, wherein the at least one parameter of the test semiconductor device is substantially the same as the at least one parameter of the device layout;

modifying the device layout of the input file when the at least one parameter of the device layout and the at least one parameter of the test semiconductor device both violate the at least one hot spot rule to avoid violating the at least one hot spot rule, wherein the device layout is modified based upon a plurality of modification guidance parameters that are associated with the plurality of hot spot rules;

creating an output file based on the modified device layout; and

fabricating a production semiconductor device corresponding to the output file.

19. The method of claim 18, wherein the input file and the output file are in a computer aided design format and wherein the modifying the device layout is performed at least partially using a computer-aided system.