IC chip design modeling using perimeter density to electrical characteristic correlation

• US 7,805,693 B2
• Filed: 02/15/2008
• Issued: 09/28/2010
• Est. Priority Date: 02/15/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Culp, James A., Chadwick, Laura S., Polson, Anthony D.
• Primary Examiner(s): Levin; Naum B
• Application Number:
  US12/031,734
• Publication Number:
  US 20090210834A1
• Time in Patent Office: 956 Days
• Field of Search: 716 4- 6, 716/8, 703/14
• US Class Current: 716/111
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.

Claims

1. A method comprising:

determining, on at least one computing device, a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design;

correlating, on the at least one computing device, a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and

modeling, on the at least one computing device, the IC chip design based on the correlation.

2. The method of claim 1, further comprising generating, on the at least one computing device, a visual representation of the perimeter density.

3. The method of claim 1, further comprising generating, on the at least one computing device, a visual representation of the perimeter density compared to the electrical characteristic.

4. The method of claim 1, wherein the measured electrical characteristic is measured using a performance screen ring oscillator (PSRO) in a respective region of the IC chip.

5. The method of claim 1, wherein the perimeter density determining includes:

determining, on the at least one computing device, the perimeter density in successively larger radii about a center of the respective region, wherein the center is a location where the measured electrical characteristic is measured.

6. A system comprising:

a perimeter density determinator for determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design;

a correlator for correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and

a modeler for modeling the IC chip design based on the correlation.

7. The system of claim 6, further comprising a visual representation generator for generating a visual representation of the perimeter density.

8. The system of claim 6, further comprising a visual representation generator for generating a visual representation of the perimeter density compared to the electrical characteristic.

9. The system of claim 6, further comprising an electrical characteristic measuring system including a performance screen ring oscillator (PSRO) in a respective region of the IC chip.

10. The system of claim 6, wherein the perimeter density determinator determines the perimeter density in successively larger radii about a center of the respective region, wherein the center is a location where the measured electrical characteristic is measured.

11. A computer program comprising program code embodied in at least one computer-readable storage medium, which when executed, enables a computer system to implement a method of modeling an integrated circuit (IC) chip design, the method comprising:

determining a perimeter density of conductive structure within each region of a plurality of regions of the IC chip design;

correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and

for modeling the IC chip design based on the correlation.

12. The computer program of claim 11, further comprising generating a visual representation of the perimeter density.

13. The computer program of claim 11, further comprising generating a visual representation of the perimeter density compared to the electrical characteristic.

14. The computer program of claim 11, further comprising measuring an electrical characteristic using a performance screen ring oscillator (PSRO) in a respective region of the IC chip.

15. The computer program of claim 11, wherein determining the perimeter density determines the perimeter density in successively larger radii about a center of the respective region, wherein the center is the location of the electrical characteristic measurement.