System and method for protection of data contained in an integrated circuit

• US 7,806,319 B2
• Filed: 04/11/2006
• Issued: 10/05/2010
• Est. Priority Date: 04/11/2005
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Pomet, Alain, Romain, Fabrice
• Primary Examiner(s): Le; Thien Minh
• Assistant Examiner(s): VO, TUYEN KIM
• Application Number:
  US11/402,650
• Publication Number:
  US 20070043993A1
• Time in Patent Office: 1,638 Days
• Field of Search: 235/375, 235/380, 235/451, 235/492, 711/163, 711/164
• US Class Current: 235/380
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: H04L 9/004 for fault attacks

Abstract

A method and a circuit for protecting an integrated circuit against an extraction of data read from at least one memory, comprising the steps of comparing each data word to be output from the integrated circuit with at least one value stored in this circuit, and generating an error signal in case of an identity between the value and the data waiting to be output.

Claims

1. A method for protecting an integrated circuit against an extraction of data read from at least one memory, comprising the steps of:

comparing each data word to be output from the integrated circuit with at least one value stored in this circuit, each value being stored in the memory at an address which is not likely to be requested by programs providing data to the outside of the circuit;

determining whether identity exists between each value and each data word waiting to be output; and

generating an error signal if identity is determined to exist.

2. The method of claim 1, wherein said value is stored in an element distinct from said memory.

3. The method of claim 2, wherein said value is stored in non-volatile fashion.

4. The method of claim 1, wherein the address of a data word to be read from the memory to be provided to the outside of the circuit is compared with at least one address stored in the circuit, said error signal being generated if identity between the two addresses is determined.

5. A method of protecting data stored in an integrated circuit against undesired output of that data from the integrated circuit, the method comprising:

storing at least one value in the integrated circuit, each value being stored at a plurality of locations in the integrated circuit with each location being a location that is unlikely to be accessed during the output of data from the integrated circuit;

for data to be output from the integrated circuit, comparing the data to at least one value stored in the integrated circuit; and

when the operation of comparing indicates the data equals one of the stored values, prohibiting the output of the data from the integrated circuit.

6. The method of claim 5, wherein the data being compared to the predetermined values comprises an address associated with a data word stored in the integrated circuit.

7. The method of claim 6, wherein the data being compared comprises both the address and the data word, with the address being compared to predetermined address values and the data word being compared to predetermined data word values.

8. The method of claim 5, wherein prohibiting the output of the data word from the integrated circuit includes generating an error signal.

9. The method of claim 5, wherein each location comprises non-volatile memory storage location.

11. The method of claim 5, wherein each value is stored in an element distinct from said memory.

10. A method of protecting data stored in an integrated circuit against undesired output of that data from the integrated circuit, the method comprising:

storing at least one value in the integrated circuit, each value being stored at a plurality of locations in the integrated circuit with each location being a location that is unlikely to be accessed during the output of data from the integrated circuit;

for data to be output from the integrated circuit, comparing the data to at least one value stored in the integrated circuit;

when the operation of comparing indicates the data equals one of the stored values, prohibiting the output of the data from the integrated circuit; and

wherein the values stored in the integrated circuit have predetermined values determined by a user of the integrated circuit.

12. An integrated circuit, comprising:

a processor;

a memory coupled to the processor, the memory operable to store data words; and

an input/output circuit coupled to the processor, the input/output circuit operable to compare data words received from the memory via the processor to at least one prohibited value, each prohibited value being stored in a plurality of storage locations in the integrated circuit and the input/output circuit operable to prevent the data word from being output from the integrated circuit responsive to the data word being equal to one of the prohibited values.

16. The integrated circuit of claim 12, wherein the integrated circuit is embodied in a smart card.

17. The integrated circuit of claim 16, wherein the smart card is a telephone calling or electronic cash payments smart card.

18. The integrated circuit of claim 12, wherein the input/output circuit includes storage locations and the prohibited values are stored in these storage locations in the input/output circuit.

19. The integrated circuit of claim 18, wherein the prohibited values have values with a low probability of occurring in other data words stored in the memory.

20. The integrated circuit of claim 12, wherein the prohibited values are stored in storage locations in the memory.

13. An integrated circuit, comprising:

a processor;

a memory coupled to the processor, the memory operable to store data words;

an input/output circuit coupled to the processor, the input/output circuit operable to compare data words received from the memory via the processor to at least one prohibited value, each prohibited value being stored in a plurality of storage locations in the integrated circuit and the input/output circuit operable to prevent the data word from being output from the integrated circuit responsive to the data word being equal to one of the prohibited values; and

wherein the input/output circuit comprises;

at least one storage element, each storage element storing a respective prohibited value; and

a comparator coupled to each storage element and to the processor, the comparator coupled to receive data words from the processor and operable to compare the data words to the prohibited values in the storage elements and to generate an alarm signal responsive to the data word being equal to any of the prohibited values.

14. The integrated circuit of claim 13, wherein the storage element and comparator are physically positioned adjacent circuitry in the input/output circuitry that outputs data words from the integrated circuit.

15. The integrated circuit of claim 13, wherein each data word stored in the memory has an associated address and wherein the prohibited values include prohibited address values, and wherein the comparator is further operable to compare the address of each data word to the prohibited address values and to generate the alarm signal responsive to the address being equal to any of the prohibited address values.