Method for transferring wafers

• US 7,807,482 B2
• Filed: 06/02/2005
• Issued: 10/05/2010
• Est. Priority Date: 06/02/2004
• Status: Active Grant

• Current Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Original Assignee: Soitec Silicon On Insulator Technologies SA (Soitec S.A.)
• Inventors: Lagahe-Blanchard, Chrystelle, Aspar, Bernard
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US11/628,615
• Publication Number:
  US 20080254596A1
• Time in Patent Office: 1,951 Days
• Field of Search: 438 15- 20, 438106-113, 438455-485, 257/E21.122, 257/238, 257/505, 257/599, 257/705, 257/E25.012
• US Class Current: 438/15
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Abstract

The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.

Claims

1. Method for transfer onto a substrate of a thin layer or of a chip, this thin layer or this chip being supported by a support wafer and presenting a surface topology, therefore variations in height or level according to a direction perpendicular to a plane defined by the thin layer, this method including:

the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer, and of at least one layer, called first barrier layer, the adhesive layer being in a material of which etching presents selectivity in relation to the material of the barrier layer,

the transfer of the thin layer or of the chip onto said substrate,

elimination of adhesive layers and of the first barrier layer, to find the initial topology again.

2. Method according to claim 1, the transfer including a prior assembly of the adhesive layer with a handle substrate, as well as the elimination of all or part of the support wafer.

3. Method according to claim 2, further comprising the elimination of the handle substrate.

4. Method according to claim 1, the first barrier layer being made of a material of which etching presents selectivity in relation to the material beneath this barrier layer.

5. Method according to claim 1, the first barrier layer having a thickness between 10 nm and 500 nm and/or conformal with the surface of said thin layer or of said chip or with a thickness greater than 500 nm and is conformal with the surface of said thin layer or said chip.

6. Method according to claim 1, the variation(s) in level being between 10 nm and 5 μ

m.

7. Method according to claim 1, the surface of the thin layer or of the chip including electrical contact zones.

8. Method according to claim 1, the adhesive layer being of a mineral type.

9. Method according to claim 1, the adhesive layer being made of silicon dioxide.

10. Method according to claim 1, the adhesive layer being of an organic type.

11. Method according to claim 1, the adhesive layer being made of BCB-type polymer, or of an adhesive substance.

12. Method according to claim 1, the material of the first barrier layer being made of nitride (Si3N4) or amorphous silicon and the material of the adhesive layer of silicon oxide (SiO2).

13. Method according to claim 1 the material of the first barrier layer being oxide (SiO₂) and the material of the adhesive layer being silicon nitride (Si3N4).

14. Method according to claim 1, the thin layer or the chip being directly beneath the barrier layer.

15. Method according to claim 14, at least one part of the surface of the thin layer or of the chip being made of an oxide or of an oxynitride or of a nitride.

16. Method according to claim 15, at least one other part of the surface of the thin layer or of the chip including contact zones.

17. Method according to claim 1, a second barrier layer, or protective layer, being present between the first barrier layer and the surface of the thin layer or of the chip.

18. Method according to claim 17, said second barrier layer being made of a material of which etching presents selectivity in relation to the surface material of the thin layer or of the chip.

19. Method according to claim 18, said second barrier layer having a thickness between 10 nm and 500 nm.

20. Method according to claim 17, said second barrier layer being made of silicon oxide (SiO2).

21. Method according to claim 1, further including a preparation step of the surface for bonding.

22. Method according to claim 1, further including the possible elimination of a second barrier layer.

23. Method according to claim 1, said bonding onto the first substrate and/or onto the second substrate being molecular bonding.

24. Method according to claim 1, the selectivity or selectivities being between 2 and 10 or between 10 and 1000 or greater than 1000.

25. Method for processing of a thin layer or of a chip, this thin layer or this chip being supported by a support wafer and presenting a surface topology, therefore variations in height or in level according to a direction perpendicular to a plane defined by the thin layer, this method including:

realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer, and of at least one layer, called first barrier layer, the adhesive layer being in a material of which etching presents selectivity in relation to the material of the barrier layer,

an assembly of the adhesive layer with a handle substrate,

elimination of all or part of the support wafer, then;

processing of the thin layer or of the chip from its face not assembled with said handle substrate,

or processing of a face of the support wafer not assembled with the thin layer or the chip,

elimination of the handle substrate,

elimination of adhesive layers and of the first barrier layer, to find the initial topology again.

26. Method according to claim 25, the processing of the thin layer or of the chip or of a face of the support wafer including a step for depositing a metallic layer and/or a lithography step and/or an etching step and/or an ion implantation step and/or a cleaning step and/or a thinning step.

27. Method according to claim 25, the first barrier layer being made of a material of which etching presents selectivity in relation to the material beneath this barrier layer.

28. Method according to claim 25, the first barrier layer having a thickness between 10 nm and 500 nm and/or conformal with the surface of said thin layer or of said chip or with a thickness greater than 500 nm and is conformal with the surface of said thin layer or said chip.

29. Method according to claim 25, the variation(s) in level being between 10 nm and 5 μ

m.

30. Method according to claim 25, the surface of the thin layer or of the chip including electrical contact zones.

31. Method according to claim 25, the adhesive layer being of a mineral type.

32. Method according to claim 31, the adhesive layer being made of silicon dioxide.

33. Method according to claim 25, the adhesive layer being of an organic type.

34. Method according to claim 33, the adhesive layer being made of BCB-type polymer, or of an adhesive substance.

35. Method according to claim 25, the material of the first barrier layer being made of nitride (Si3N4) or amorphous silicon and the material of the adhesive layer of silicon oxide (SiO2).

36. Method according to claim 25, the material of the first barrier layer being oxide (SiO₂) and the material of the adhesive layer being silicon nitride (Si3N4).

37. Method according to claim 25, the thin layer or the chip being directly beneath the barrier layer.

38. Method according to claim 37, at least one part of the surface of the thin layer or of the chip being made of an oxide or of an oxynitride or of a nitride.

39. Method according to claim 37, at least one other part of the surface of the thin layer or of the chip including contact zones.

40. Method according to claim 25, a second barrier layer, or protective layer, being present between the first barrier layer and the surface of the thin layer or of the chip.

41. Method according to claim 40, said second barrier layer being made of a material of which etching presents selectivity in relation to the surface material of the thin layer or of the chip.

42. Method according to claim 40, said second barrier layer having a thickness between 10 nm and 500 nm.

43. Method according to claim 40, said second barrier layer being made of silicon oxide (SiO2).

44. Method according to claim 25, further including a preparation step of the surface for bonding.

45. Method according to claim 25, further including the possible elimination of a second barrier layer.

46. Method according to claim 25, said bonding onto the first substrate and/or onto the second substrate being molecular bonding.

47. Method according to claim 25, the selectivity or selectivities being between 2 and 10 or between 10 and 1000 or greater than 1000.

48. Method for transfer onto a substrate of a thin layer or a chip, this thin layer or this chip being supported by a support wafer, and presenting a surface topology, therefore variations in height or level according to a direction perpendicular to a plane defined by the thin layer, the surface of this layer or of this chip including at least one layer of silicon nitride (Si3N4) or silicon oxynitride and metallic contact pads, this transfer method including:

the realization, above the surface of said thin layer or of said chip, of at least one layer, called adhesive layer made of a material of which etching presents selectivity in relation to the nitride,

the transfer of the thin layer or of the chip onto said substrate,

elimination of the adhesive layer to find the initial topology again.

49. Method according to claim 48, the transfer including prior assembly of the adhesive layer with a handle substrate, as well as the elimination of all or part of the support wafer.

50. Method according to claim 49, including, after transfer onto the substrate, the elimination of the handle substrate.

51. Method according to claim 48, further including the possible elimination of a second barrier layer.

52. Method according to claim 48, said bonding onto the first substrate and/or onto the second substrate being molecular bonding.

53. Method according to claim 48, the selectivity or selectivities being between 2 and 10 or between 10 and 1000 or greater than 1000.

54. Method according to claim 48, the adhesive layer being made of silicon dioxide or polymer.

55. Method for processing a thin layer or a chip, this thin layer or this chip being supported by a support wafer, and presenting a surface topology, therefore variations in height or level according to a direction perpendicular to a plane defined by the thin layer, the surface of this layer or of this chip including at least one layer of silicon nitride (Si3N4) or silicon oxynitride and metallic contact pads, this transfer method including:

the realization, above the surface of said thin layer or of said chip, of at least one layer, called adhesive layer, made of a material of which etching presents selectivity in relation to the nitride,

assembly of the adhesive layer with a handle substrate,

elimination of all or part of the support wafer, then;

processing of the thin layer or of the chip from its face not assembled with said handle wafer,

or processing of a face of the support wafer not assembled with the thin layer or the chip,

elimination of the handle wafer,

elimination of the adhesive layer, to find the initial topology again.

56. Method according to claim 55, the processing of the thin layer or of the chip, or of a face of the support wafer, including a step for depositing a metallic layer and/or a step of lithography and/or en etching step and/or an ion implantation and/or a cleaning step and/or a thinning step.

57. Method according to claim 55, the adhesive layer being made of silicon dioxide or polymer.

58. Method according to claim 55, further including the possible elimination of a second barrier layer.

59. Method according to claim 55, said bonding onto the first substrate and/or onto the second substrate being molecular bonding.

60. Method according to claim 55, the selectivity or selectivities being between 2 and 10 or between 10 and 1000 or greater than 1000.