Method of packaging a device having a multi-contact elastomer connector contact area and device thereof

• US 7,807,511 B2
• Filed: 11/17/2006
• Issued: 10/05/2010
• Est. Priority Date: 11/17/2006
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Burch, Kenneth R., Mangrum, Marc A.
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US11/561,234
• Publication Number:
  US 20080116573A1
• Time in Patent Office: 1,418 Days
• Field of Search: 438/106, 438/112, 438/126, 438/127, 174/521, 257/E21.499
• US Class Current: 438/127
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. A first insulating layer is formed over the first major surface. A plurality of vias are formed in the first insulating layer. A plurality of contacts are formed to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer. A supporting layer is formed over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts.

Claims

1. A method of forming a packaged device having a semiconductor device having a first major surface and a second major surface, comprising:

forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major

surface of the first semiconductor device exposed,

forming a first insulating layer over the first major surface;

forming a plurality of vias in the first insulating layer;

forming a plurality of contacts to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer and the surfaces of the plurality of contacts are in a line; and

forming a supporting layer over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts, the opening is rectangular, and the sidewall is adjacent to the plurality of contacts.

2. The method of claim 1, wherein the step of forming the supporting layer is further characterized by the sidewall being for receiving a multi-contact elastomeric connector.

3. The method of claim 1, wherein the step of forming the supporting layer comprises:

placing a connector wall over the first insulating layer and around the plurality of contacts having a first face toward the plurality of contacts and a second face away from the plurality of contacts, wherein the first face comprises the sidewall; and

depositing a liquid, after the step of placing the connector wall, over the first insulating layer so that liquid is adjacent to the second face and prevented from reaching the first face; and

curing the liquid for completing formation of the supporting layer.

4. The method of claim 1, wherein the step of forming the supporting layer comprises:

forming a polymer-based dielectric layer over the first insulating layer; and

etching the opening in the polymer-based dielectric layer.

5. The method of claim 1, wherein the step of forming the supporting layer comprises:

applying a mold over the first insulating layer that prevents mold compound from being applied to the plurality of contacts;

applying the mold compound to the mold; and

curing the mold compound to form the supporting layer.

6. The method of claim 1, further comprising filling the opening with a gel.

7. The method of claim 3, wherein the step of depositing the liquid is further characterized by the liquid comprising an epoxy resin.

8. The method of claim 7, wherein the step of placing the connector wall is further characterized by the connector wall comprising plastic.

9. A packaged semiconductor device comprising

a semiconductor device having a first major surface and a second major surface;

an encapsulant over the second major surface and around sides of the semiconductor device,

a first insulating layer over the first major surface;

a plurality of vias in the first insulating layer;

a plurality of contacts to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer and the plurality of contacts are in a line; and

a supporting layer over the first insulating layer having an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts, the opening is rectangular, and the sidewall is adjacent to the plurality of contacts.

10. The packaged semiconductor device of claim 9, wherein the sidewall comprises means for receiving a multi-contact elastomeric connector.

11. The packaged semiconductor device of claim 9, further comprising a connector wall over the first insulating layer and around the plurality of contacts having a first face toward the plurality of contacts and a second face away from the plurality of connectors, wherein the first face comprises the sidewall.

12. The packaged semiconductor device of claim 11, wherein the plurality of contacts make contact to surface contacts on the first surface of the semiconductor device.

13. A method of forming a packaged device having a semiconductor device having a first major surface and a second major surface, comprising:

forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed;

forming a first insulating layer over the first major surface;

forming a plurality of vias in the first insulating layer;

forming a plurality of contacts to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer; and

forming a supporting layer over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall means for receiving a multi-contact elastomeric connector, the opening is rectangular, the sidewall is adjacent to the plurality of contacts, and the plurality of contacts are in a line.

14. The method of claim 13, wherein the step of forming the supporting layer comprises:

placing a connector wall over the first insulating layer and around the plurality of contacts having a first face toward the plurality of contacts and a second face away from the plurality of connectors, wherein the first face comprises the sidewall;

depositing a liquid, after the step of placing the connector wall, over the first insulating layer so that liquid is adjacent to the second face and prevented from reaching the first face; and

curing the liquid for completing formation of the supporting layer.

15. The method of claim 13, wherein the step of forming the supporting layer comprises:

forming a second insulating layer over the first insulating layer; and

etching the opening in the second insulating layer.

16. The method of claim 13, wherein the step of forming the supporting layer comprises:

applying a mold over the first insulating layer that prevents mold compound from being applied to the plurality of contacts; and

applying the mold compound to the mold; and

curing the mold compound to form the supporting layer.