Method for forming non-volatile memory with shield plate for limiting cross coupling between floating gates

• US 7,807,533 B2
• Filed: 02/01/2008
• Issued: 10/05/2010
• Est. Priority Date: 02/13/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Lutze, Jeffrey W.
• Primary Examiner(s): Brewster; William M
• Application Number:
  US12/024,787
• Publication Number:
  US 20080124865A1
• Time in Patent Office: 977 Days
• Field of Search: 438/264, 438/296, 257/E21.409
• US Class Current: 438/264
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory system is disclosed that includes a set of non-volatile storage elements. Each of the non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned between adjacent floating gate stacks and electrically connected to the source/drain regions for reducing coupling between adjacent floating gates. The shield plates are selectively grown on the active areas of the memory without being grown on the inactive areas. In one embodiment, the shield plates are epitaxially grown silicon positioned above the source/drain regions.

Claims

1. A method of forming non-volatile memory, comprising:

forming a first dielectric layer above a substrate;

forming a first layer of gate material above the first dielectric layer;

forming a second dielectric layer above the first layer of gate material;

forming a second layer of gate material above the second dielectric layer;

forming floating gate stacks from the first dielectric layer, first layer of gate material, second dielectric layer and second layer of gate material, a floating gate is provided by the first layer of gate material in each of the floating gate stacks;

forming source/drain regions between pairs of adjacent floating gate stacks, where the floating gate stacks and the source/drain regions are formed in a plurality of NAND strings extending parallel to one another in an array; and

forming shallow trench isolation regions in the substrate which extend parallel to one another in strips alongside the NAND strings, the shallow trench isolation regions also extend parallel to the NAND strings;

forming word lines which extend parallel to one another in the array, where the word lines are connected to the floating gate stacks;

performing a selective epitaxial process to grow shield layers on the source/drain regions between the pairs of adjacent floating gate stacks, the shield layers are grown on the source/drain regions between each pair of adjacent floating gate stacks within each NAND string, and are not grown above the shallow trench isolation regions, the shield layers extend to a height which is above a top of the first dielectric layer and above a bottom portion of the first layer of gate material, the height is partway between a top and bottom of the floating gate in each floating gate stack, so that the shield layers act as shield plates which reduce capacitive coupling between floating gates of each pair of adjacent floating gate stacks.

2. The method of claim 1, wherein:

the shield layers are epitaxially grown layers of silicon.

3. The method of claim 2, wherein:

the step of forming source/drain regions includes implanting ions into the substrate between floating gate stacks; and

the method further includes implanting ions into the epitaxially grown shield layer.

4. The method of claim 1, wherein:

the forming shallow trench isolation regions includes etching the first layer of gate material, the first dielectric area and the substrate to form shallow trench areas, and filling the shallow trench areas with dielectric material.

5. The method of claim 1, wherein:

the shield layers are self aligned shield plates.

6. The method of claim 1, wherein the shield layers are electrically connected to the source/drain regions, the method further comprising:

providing insulating material covering each shield layer so that the shield layers do not have any electrical connection other than to the source/drain regions.

7. The method of claim 1, wherein:

the step of forming a first dielectric layer includes growing tunnel oxide;

the steps of forming a first layer of gate material includes depositing polysilicon;

the step of forming a second dielectric layer includes depositing ONO;

the step of forming a second layer of gate material includes depositing polysilicon; and

the step of forming source/drain regions includes implanting ions into the substrate between floating gate stacks.

8. The method of claim 7, wherein:

the forming shallow trench isolation regions includes;

adding an active area mask;

etching the first layer of gate material, the dielectric area and the substrate based on the active area mask to form shallow trench areas; and

filling the shallow trench areas with dielectric material; and

the method further includes etching the second layer of gate material and the second dielectric layer to form the floating gate stacks.

9. The method of claim 1, further comprising:

oxidizing sidewalls of the floating gate stacks;

depositing oxide spacer material on the floating gate stacks; and

etching the oxide spacer material to form oxide spacers at the sidewalls of the floating gate stacks, the shield layers extend upwards between the oxide spacers.

10. The method of claim 9, further comprising:

depositing nitride spacer material along the oxide spacers and on the shield layers; and

etching the nitride spacer material to form nitride spacers along the oxide spacers, the nitride spacers contact top portions of the shield layers.

11. The method of claim 10, further comprising:

providing an insulating material to fully cover top portions of each shield layer which are not contacted by the nitride spacers.

12. The method of claim 1, further comprising:

forming first spacers at sidewalls of the floating gate stacks, the shield layers extend upwards between the first spacers; and

forming second spacers along the first spacers after the shield layers are epitaxially grown, bottom portions of the second spacers contact top portions of the shield layers.

13. The method of claim 1, further comprising:

providing sidewall insulating material on sidewalls of the floating gate stacks, the shield layers are positioned between the sidewall insulating material of each pair of adjacent floating gate stacks; and

providing insulating material which covers top portions of the shield layers.

14. The method of claim 1, wherein:

a control gate is provided by the second layer of gate material in each of the floating gate stacks.

19. The method of claim 1, wherein:

the shield layers are positioned only on the source/drain regions.

20. The method of claim 1, wherein:

the substrate comprises a triple well including a P substrate, an N-well and a P-well, and the source/drains are within the P-well.

21. The method of claim 1, wherein:

the growing epitaxial portions include growing 600 Angstroms of an epitaxial silicon layer.

15. A method of forming non-volatile memory, comprising:

forming a set of non-volatile storage elements on a substrate, each memory element comprising a control gate and a floating gate, the substrate comprises a triple well including a P substrate, an N-well and a P-well;

forming source/drain regions between the non-volatile storage elements, and within the P-well, the non-volatile storage elements and the source/drain regions are formed in a plurality of NAND strings extending parallel to one another;

forming shallow trench isolation regions in the substrate which extend parallel to one another in strips alongside the NAND strings, the shallow trench isolation regions also extend parallel to the NAND strings;

forming word lines which extend parallel to one another, where the word lines are connected to the non-volatile storage elements; and

growing epitaxial portions on the source/drain regions, but not above the shallow trench isolation regions, the epitaxial portions extend to a height which is partway between top and bottom portions of the floating gates to reduce coupling between adjacent floating gates.

16. The method of claim 15, wherein the epitaxial portions are electrically connected to the source/drain regions, the method further comprising:

providing insulating material covering each epitaxial portion so that the epitaxial portions do not have any electrical connection other than to the source/drain regions.

17. The method of claim 15, further comprising:

forming first spacers at sidewalls of the non-volatile storage elements, the epitaxial portions extend upwards between the first spacers; and

forming second spacers along the first spacers after the epitaxial portions are epitaxially grown, portions of the second spacers contact top portions of the epitaxial portions.

18. The method of claim 17, further comprising:

providing an insulating material to fully cover top portions of each epitaxial portion which are not contacted by the bottom portions of second spacers.

22. The method of claim 15, wherein:

the epitaxial portions are grown only on the source/drain regions.

23. The method of claim 15, wherein:

the growing epitaxial portions include growing 600 Angstroms of an epitaxial silicon layer.