Low resistance gate for power MOSFET applications and method of manufacture

• US 7,807,536 B2
• Filed: 08/29/2006
• Issued: 10/05/2010
• Est. Priority Date: 02/10/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation), Telesector Resources Group Incorporated
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sreekantham, Sreevatsa, Naylor, Kent, Ho, Ihsiu, Session, Fred
• Primary Examiner(s): Wilczewski; Mary
• Assistant Examiner(s): Thomas; Toniae M
• Application Number:
  US11/467,997
• Publication Number:
  US 20070190728A1
• Time in Patent Office: 1,498 Days
• Field of Search: 438/209, 438/212, 438/268, 438/270, 438/589, 438/677, 257/333, 257/409, 257/E21.41
• US Class Current: 438/270
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.

Claims

1. A method of forming a trench gate field effect transistor, comprising:

forming a trench in a semiconductor region that comprises a substrate of a first conductivity type and a silicon region of the first conductivity type over the substrate, the silicon region having a lower doping concentration than the substrate;

forming a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench;

forming a conductive seed layer in a bottom portion of the trench over the dielectric layer;

growing a low resistance material over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer; and

forming a well region of a second conductivity type in the silicon region, wherein the conductive seed layer has an upper surface below a bottom surface of the well region.

2. The method of claim 1 wherein the conductive seed layer and low resistance material form at least part of a gate electrode.

3. The method of claim 1 further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer corresponding to the silicon region,

wherein the well region of a second conductivity type is formed in the epitaxial layer; and

forming source regions of the first conductivity type in the well region adjacent the trench.

4. The method of claim 1 wherein the step of forming a conductive seed layer comprises:

depositing a polysilicon layer, filling the trench; and

recessing the polysilicon layer in the trench.

5. The method of claim 4 wherein the polysilicon layer is in-situ doped to be made more conductive.

6. The method of claim 1 wherein the conductive seed layer comprises one of metal and metal compound.

7. The method of claim 1 further comprising:

prior to forming the conductive seed layer, forming a thick bottom dielectric along the bottom of the trench.

8. A method of forming a shielded gate field effect transistor, comprising:

forming a trench in a semiconductor region that comprises a substrate of a first conductivity type and a silicon region of the first conductivity type over the substrate, the silicon region having a lower doping concentration than the substrate;

lining lower sidewalls and bottom of the trench with shield dielectric;

filling a lower portion of the trench with a shield electrode;

forming an inter-electrode dielectric over the shield electrode;

forming a dielectric layer lining upper trench sidewalls and extending over mesa regions adjacent the trench;

forming a conductive seed layer over the inter-electrode dielectric layer;

growing a low resistance material over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer; and

forming a well region of a second conductivity type in the silicon region, wherein the conductive seed layer has an upper surface below a bottom surface of the well region.

9. The method of claim 8 wherein the conductive seed layer and low resistance material form at least part of a gate electrode.

10. The method of claim 8 further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer corresponding to the silicon region,

wherein the well region of a second conductivity type is formed in the epitaxial layer; and

forming source regions of the first conductivity type in the well region adjacent the trench.

11. The method of claim 8 wherein the step of forming a conductive seed layer comprises:

depositing a polysilicon layer, filling the trench; and

recessing the polysilicon layer in the trench.

12. The method of claim 11 wherein the polysilicon layer is in-situ doped to be made more conductive.

13. The method of claim 8 wherein the conductive seed layer comprises one of metal and metal compound.

14. The method of claim 8 wherein the dielectric layer is a gate dielectric layer, and the shield dielectric has a greater thickness than the gate dielectric layer.

15. A method of forming a trench gate field effect transistor, comprising:

forming trenches in a semiconductor region;

forming a dielectric layer lining sidewalls and bottom of each trench and extending over mesa regions adjacent the trenches;

forming a conductive seed layer in a bottom portion of each trench over the dielectric layer; and

growing a low resistance material over the conductive seed layer in each trench, wherein the low resistance material is selective to the conductive seed layer and is grown to a height below a top surface of the mesa regions adjacent the trenches.

16. The method of claim 15 wherein the conductive seed layer and low resistance material form at least part of a gate electrode in each trench.

17. The method of claim 15 wherein the semiconductor region comprises a substrate of a first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the epitaxial layer forming an upper part of the semiconductor region;

forming a well region of a second conductivity type in the epitaxial layer; and

forming source regions of the first conductivity type in the well region adjacent the trenches.

18. The method of claim 15 wherein the step of forming a conductive seed layer comprises:

depositing a polysilicon layer, filling each trench; and

recessing the polysilicon layer in each trench.

19. The method of claim 18 wherein the polysilicon layer is in-situ doped to be made more conductive.

20. The method of claim 15 wherein the conductive seed layer comprises one of metal and metal compound.

21. The method of claim 15 further comprising:

prior to forming the conductive seed layer, forming a thick bottom dielectric along the bottom of each trench.

22. A method of forming a shielded gate field effect transistor, comprising:

forming trenches in a semiconductor region;

lining lower sidewalls and bottom of each trench with a shield dielectric;

filling a lower portion of each trench with a shield electrode;

forming a dielectric layer over the shield electrode in each trench;

forming a conductive seed layer in each trench over the dielectric layer; and

growing a low resistance material over the conductive seed layer in each trench, wherein the low resistance material is selective to the conductive seed layer and is grown to a height below a top surface of the mesa regions adjacent the trenches.

23. The method of claim 22 wherein the conductive seed layer and the low resistance material form at least part of a gate electrode in each trench.

24. The method of claim 22 wherein the semiconductor region comprises a substrate of a first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the epitaxial layer forming an upper part of the semiconductor region;

forming a well region of a second conductivity type in the epitaxial layer; and

forming source regions of the first conductivity type in the well region adjacent the trenches.

25. The method of claim 22 wherein the step of forming a conductive seed layer comprises:

depositing a polysilicon layer, filling each trench; and

recessing the polysilicon layer in each trench.

26. The method of claim 25 wherein the polysilicon layer is in-situ doped to be made more conductive.

27. The method of claim 22 wherein the conductive seed layer comprises one of metal and metal compound.