Solar cell fabrication using extrusion mask

• US 7,807,544 B2
• Filed: 09/14/2009
• Issued: 10/05/2010
• Est. Priority Date: 12/12/2006
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Eldershaw, Craig
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US12/559,465
• Publication Number:
  US 20100003812A1
• Time in Patent Office: 386 Days
• Field of Search: 438/401, 438/462, 438/975, 438/E21.24
• US Class Current: 438/401
• CPC Class Codes: H01L 31/022425 for solar cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature

Abstract

Large-area ICs (e.g., silicon wafer-based solar cells) are produced by positioning a mask between an extrusion head and the IC wafer during extrusion of a dopant bearing material or metal gridline material. The mask includes first and second peripheral portions that are positioned over corresponding peripheral areas of the wafer, and a central opening that exposes a central active area of the wafer. The extrusion head is then moved relative to the wafer, and the extrusion material is continuously extruded through outlet orifices of the extrusion head to form elongated extruded structures on the active area of the wafer. The mask prevents deposition of the extrusion material along the peripheral edges of the wafer, and facilitates the formation of unbroken extrusion structures. The mask may be provided with a non-rectangular opening to facilitate the formation of non-rectangular (e.g., circular) two-dimensional extrusion patterns.

Claims

1. A method for fabricating an integrated circuit on a semiconductor substrate, the method comprising:

aligning a mask between an extrusion head and the semiconductor substrate such that a first peripheral portion of the mask is positioned over a first peripheral area of the semiconductor substrate, a second peripheral portion of the mask is positioned over a second peripheral area of the semiconductor substrate, and a central opening defined between the first and second peripheral portions is positioned over a central area of the semiconductor substrate disposed between the first and second peripheral areas;

moving the extrusion head relative to the semiconductor substrate such that a plurality of outlet orifices defined in the extrusion head are moved from a first position over the first peripheral area to a second position over the second peripheral area, whereby such the plurality of outlet orifices pass over the central area of the semiconductor substrate; and

extruding a material such that said material is continuously extruded through the plurality of outlet orifices while the extrusion head is moved from the first position to the second position, whereby the extruded material forms a plurality of elongated extruded structures on the central area of the semiconductor substrate.

2. The method of claim 1, wherein controlling extrusion comprises initiating said extrusion when the extrusion head is in the first position, and terminating said extrusion when the extrusion head is in the second position.

3. The method of claim 1, further comprising heating the plurality of elongated extruded structures such that a dopant contained in said plurality of elongated extruded structures diffuses into the semiconductor substrate, thereby forming a plurality of doped regions.

4. The method according to claim 3, further comprising:

depositing a passivation layer on a surface of the semiconductor substrate over the plurality of doped regions,

laser ablating portions of the passivation layer such that a plurality of contact openings are defined through the passivation layer to each of the plurality of doped regions,

depositing a conductive contact structure into each of the contact openings using a direct-write metallization apparatus, and

depositing metal line structures onto an upper surface of the passivation layer such that each metal line structure contacts a group of said contact structures that are disposed over a corresponding one of said doped regions.

5. The method according to claim 4, wherein depositing said metal line structures comprises positioning a second mask over said substrate and extruding metal line material over said passivation layer.

6. The method according to claim 1, further comprising depositing a passivation layer on a surface of the semiconductor substrate before extruding said material.

7. The method according to claim 1, wherein aligning said mask comprises attaching said mask to said semiconductor substrate.

8. The method according to claim 1, further comprising attaching said semiconductor substrate to a carrier, wherein aligning said mask comprises attaching said mask to said carrier.

9. The method according to claim 1, further comprising attaching said semiconductor substrate to a carrier, wherein aligning said mask comprises suspending the mask between the carrier and the extrusion head.

10. The method according to claim 1, wherein aligning said mask comprises:

mounting a mask belt having a first portion wound around a first spool and a second portion wound around a second spool, and

rotating the first and second spools such that a mask opening defined in the mask belt is positioned over the central area of the semiconductor substrate.

11. The method according to claim 10, wherein the mask belt defines a large mask opening and a small mask opening, and

wherein aligning said mask comprises:

positioning the mask belt such that the large mask opening is located over a carrier;

placing said semiconductor substrate on said carrier through said large mask opening; and

positioning the mask belt such that the small mask opening is located over the semiconductor substrate prior to extruding said material.

19. The method according to claim 1, further comprising attaching said semiconductor substrate to a carrier prior to aligning said mask, wherein aligning said mask comprises attaching said mask to said carrier.

12. A method for fabricating an integrated circuit on a semiconductor substrate, the method comprising:

aligning a mask between an extrusion head and the semiconductor substrate such that a first peripheral portion of the mask is positioned over a first peripheral area of the semiconductor substrate, and a central opening defined by the first peripheral portions is positioned over a central area of the semiconductor substrate;

moving the extrusion head relative to the semiconductor substrate such that a plurality of outlet orifices defined in the extrusion head are moved from a first position over the first peripheral area to a second position, whereby such the plurality of outlet orifices pass over the central area of the semiconductor substrate; and

extruding a material such that said material is continuously extruded through the plurality of outlet orifices while the extrusion head is moved from the first position to the second position, whereby the extruded material forms a plurality of elongated extruded structures on the central area of the semiconductor substrate.

13. The method of claim 12, wherein controlling extrusion comprises initiating said extrusion when the extrusion head is in the first position, and terminating said extrusion after said plurality of outlet orifices have passed over the central area.

14. The method of claim 12, further comprising heating the plurality of elongated extruded structures such that a dopant contained in said plurality of elongated extruded structures diffuses into the semiconductor substrate, thereby forming a plurality of doped regions.

15. The method according to claim 14, further comprising:

depositing a passivation layer on a surface of the semiconductor substrate over the plurality of doped regions,

laser ablating portions of the passivation layer such that a plurality of contact openings are defined through the passivation layer to each of the plurality of doped regions,

depositing a conductive contact structure into each of the contact openings using a direct-write metallization apparatus, and

depositing metal line structures onto an upper surface of the passivation layer such that each metal line structure contacts a group of said contact structures that are disposed over a corresponding one of said doped regions.

16. The method according to claim 15, wherein depositing said metal line structures comprises positioning a second mask over said substrate and extruding metal line material over said passivation layer.

17. The method according to claim 12, further comprising depositing a passivation layer on a surface of the semiconductor substrate before extruding said material.

18. The method according to claim 12, wherein aligning said mask comprises attaching said mask to said semiconductor substrate.

20. The method according to claim 12, further comprising attaching said semiconductor substrate to a carrier, wherein aligning said mask comprises suspending the mask between the carrier and the extrusion head.