Frequency doubling using spacer mask

• US 7,807,578 B2
• Filed: 10/19/2007
• Issued: 10/05/2010
• Est. Priority Date: 06/01/2007
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Horioka, Keiji, Bencher, Christopher D.
• Primary Examiner(s): Lee; Hsien-ming
• Assistant Examiner(s): Swanson; Walter H
• Application Number:
  US11/875,250
• Publication Number:
  US 20080299776A1
• Time in Patent Office: 1,082 Days
• Field of Search: 438/703, 257/E21.249
• US Class Current: 438/703
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks

Abstract

A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. Next, the spacer mask is cropped. Finally, the sacrificial mask is removed to provide a cropped spacer mask. The cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask.

Claims

1. A method for fabricating a semiconductor mask, comprising:

providing a semiconductor stack having a sacrificial mask comprised of a series of lines, each line of said series of lines having sidewalls and ends;

depositing a spacer layer above said semiconductor stack and conformal with said sacrificial mask;

etching said spacer layer, the etching to provide a spacer mask having spacer lines adjacent to the sidewalls of each line of said series of lines of said sacrificial mask and portions of said spacer mask wrapping around the ends of each line of said series of lines, and to expose a top surface of said sacrificial mask, wherein the spacer lines adjacent to the sidewalls of each line of the series of lines of said sacrificial mask are discontinuous from the spacer lines adjacent to the sidewalls of all of the other lines of the series of lines of said sacrificial mask;

depositing and patterning a photoresist layer above said spacer mask and said sacrificial mask to form exposed portions of said spacer mask wrapping around the ends of each line of said series of lines;

etching the exposed portions of said spacer mask to crop said spacer mask by removing the portions of said spacer mask wrapping around the ends of each line of said series of lines; and

, subsequent to etching said spacer mask,

removing said sacrificial mask to provide a cropped spacer mask.

2. The method of claim 1 wherein said spacer layer is comprised substantially of silicon, wherein a top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon oxide, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of Cl₂ and HBr.

3. The method of claim 2 wherein removing said sacrificial mask to provide said cropped spacer mask comprises using an etch process selected from the group consisting of a hot H₃PO₄ wet etch, an aqueous hydrofluoric acid wet etch and a SiCoNi etch.

4. The method of claim 1 wherein said spacer layer is comprised substantially of silicon oxide, wherein a top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of C₄F₈ and CHF₃.

5. The method of claim 4 wherein removing said sacrificial mask to provide said cropped spacer mask comprises using an etch process selected from the group consisting of a hot H₃PO₄ wet etch, a SiCoNi etch, a Cl₂ plasma etch and a CF₄/O₂ plasma etch.

6. The method of claim 1 wherein said spacer layer is comprised substantially of silicon nitride, wherein a top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon oxide and silicon, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of CH₂F₂ and CHF₃.

7. The method of claim 6 wherein removing said sacrificial mask to provide said cropped spacer mask comprises using an etch process selected from the group consisting of an aqueous hydrofluoric acid wet etch, a SiCoNi etch, a Cl₂ plasma etch and a CF₄/O₂ plasma etch.

8. The method of claim 1 wherein a frequency of spacer lines is double a frequency of said series of lines of said sacrificial mask.

9. The method of claim 8 wherein a pitch of said series of lines of said sacrificial mask is approximately 4.

10. The method of claim 1, further comprising:

transferring an image of said cropped spacer mask to a mask stack, wherein said mask stack is in said semiconductor stack below said sacrificial mask, and wherein said mask stack comprises a layer of amorphous carbon film.