Image sensor having reduced well bounce

• US 7,807,955 B2
• Filed: 05/30/2008
• Issued: 10/05/2010
• Est. Priority Date: 05/30/2008
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Eastman Kodak Company
• Inventors: Shi, Gang, Parks, Christopher
• Primary Examiner(s): Luu; Thanh X
• Assistant Examiner(s): BENNETT, JENNIFER D
• Application Number:
  US12/129,999
• Publication Number:
  US 20090294631A1
• Time in Patent Office: 858 Days
• Field of Search: 250/208.1, 250/214.R, 250/214.1, 250/206, 348/272, 348302-308, 348/312, 257/257, 257/258, 257/288, 257/290, 257/291
• US Class Current: 250/214.00R
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 25/709 Circuitry for control of the power supply
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

Abstract

A CMOS image sensor or other type of image sensor comprises a pixel array and sampling and readout circuitry associated with the pixel array. In conjunction with readout of one or more pixels in a selected group of pixels of the pixel array, a pixel power line signal of the array transitions from an inactive state to an active state, and a reset signal of a non-selected group of pixels of the pixel array transitions from an active state to an inactive state within a predetermined time prior to the transition of the pixel power line signal from its inactive state to its active state. This arrangement advantageously reduces well bounce in the image sensor. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Claims

1. An image sensor comprising:

a pixel array including

a plurality of pixels with at least one pixel comprising a first transistor having a gate terminal adapted to receive a transfer signal disposed between a photosensitive element and a floating diffusion;

a second transistor including a gate terminal connected to the floating diffusion, a first diffusion region connected to a pixel power line, and a second diffusion region connected to a pixel output line; and

a third transistor including a gate terminal adapted to receive a reset signal disposed between the floating diffusion and the first diffusion region, wherein one or more pixels are connected to the second and third transistors and each photosensitive element, floating diffusion, first diffusion region, and second diffusion region are formed in a well of a first conductivity type; and

sampling and readout circuitry associated with the pixel array;

wherein in conjunction with readout of one or more pixels in a selected group of pixels of the pixel array, a pixel power line signal of the array transitions from an inactive state to an active state, and a reset signal of a non-selected group of pixels of the pixel array transitions from an active state to an inactive state within a predetermined time prior to the pixel power line signal transitioning from its inactive state to its active state, and wherein said image sensor is configured to satisfy a charge balance equation given by;

C_RGΔ

V_RG+C_PPΔ

V_PP≅

0,

where C_RG is capacitance between the gate terminal of the third transistor and the well, C_PP is capacitance between the pixel power line and the well, Δ

V_RG is a change in voltage level of the reset signal in said transition from its active state to its inactive state, and Δ

V_PP is a change in voltage level of the pixel power line signal in said transition from its inactive state to its active state.

2. The image sensor of claim 1 wherein the sampling and readout circuitry comprises a controllable signal generator coupled to the pixel array and configured to generate at least one of the pixel power line signal and the reset signal.

3. The image sensor of claim 1 wherein well of the first conductivity type is on a substrate of a second conductivity type.

4. The image sensor of claim 1 wherein the predetermined time prior to the transition of the pixel power line signal from its inactive state to its active state is less than or equal to approximately 500 nanoseconds.

5. The image sensor of claim 1 wherein the pixel power line signal transitions from its active state to its inactive state in conjunction with completion of said readout of one or more of the pixels, and the reset signal transitions from its inactive state to its active state within a predetermined time after the transition of the pixel power line signal from its active state to its inactive state.

6. The image sensor of claim 5 wherein the predetermined time after the transition of the pixel power line signal from its active state to its inactive state is less than or equal to approximately 500 nanoseconds.

7. The image sensor of claim 1 wherein said readout of one or more pixels in a selected group of pixels comprises readout of pixels in a selected row of pixels and the reset signal is applied to each of a plurality of reset transistors associated with one or more non-selected rows of pixels.

8. The image sensor of claim 1 wherein the charge balance equation is satisfied if the two magnitudes |C_RGΔ

V_RG| and |C_PPΔ

V_PP| are within 25% of one another.

9. The image sensor of claim 3 wherein said first, second, and third transistors comprise PMOS transistors and said well comprises an n-well formed on a p-type substrate of the image sensor.

10. The image sensor of claim 3 wherein said first, second, and third transistors comprise NMOS transistors and said well comprises a p-well formed on an n-type substrate of the image sensor.

11. A method for use with an image sensor comprising a pixel array, the method comprising:

in conjunction with readout of one or more pixels in a selected group of pixels of the pixel array, controlling a pixel power line signal of the array to transition from an inactive state to an active state, and controlling a reset signal of a non-selected group of pixels of the pixel array to transition from an active state to an inactive state within a predetermined time prior to the transition of the pixel power line signal from its inactive state to its active state;

wherein said image sensor is configured to satisfy a charge balance equation specifying estimated charge displacements in a well associated with the respective transitions in said pixel power line signal and said reset signal.

12. The method of claim 11 wherein the predetermined time prior to the transition of the pixel power line signal from its inactive state to its active state is less than or equal to approximately 500 nanoseconds.

13. The method of claim 11 further comprising controlling the pixel power line signal to transition from its active state to its inactive state in conjunction with completion of said readout of one or more of the pixels, and controlling the reset signal to transition from its inactive state to its active state within a predetermined time after the transition of the pixel power line signal from its active state to its inactive state.

14. The method of claim 13 wherein the predetermined time after the transition of the pixel power line signal from its active state to its inactive state is less than or equal to approximately 500 nanoseconds.

15. A digital imaging device comprising:

an image sensor; and

one or more processing elements configured to process outputs of the image sensor to generate a digital image;

wherein said image sensor comprises;

a pixel array including

a plurality of pixels with at least one pixel comprising a first transistor having a gate terminal adapted to receive a transfer signal disposed between a photosensitive element and a floating diffusion;

a second transistor including a gate terminal connected to the floating diffusion, a first diffusion region connected to a pixel power line, and a second diffusion region connected to a pixel output line; and

a third transistor including a gate terminal adapted to receive a reset signal disposed between the floating diffusion and the first diffusion region, wherein one or more pixels are connected to the second and third transistors; and

sampling and readout circuitry associated with the pixel array;

wherein in conjunction with readout of one or more pixels in a selected group of pixels of the pixel array, a pixel power line signal of the array transitions from an inactive state to an active state, and a reset signal of a non-selected group of pixels of the pixel array transitions from an active state to an inactive state within a predetermined time prior to the pixel power line signal transitioning from its inactive state to its active state, and wherein said image sensor is configured to satisfy a charge balance equation specifying estimated charge displacements in a well associated with the respective transitions in said pixel power line signal and said reset signal.

16. The digital imaging device of claim 15 wherein said imaging device comprises a digital camera.