Semiconductor device
First Claim
Patent Images
1. A semiconductor device comprising:
- a substrate;
a p-channel MIS transistor including;
an n-type semiconductor region formed on the substrate;
a p-type source region and a p-type drain region formed to face each other in the n-type semiconductor region;
a first insulating layer formed on the n-type semiconductor region between the p-type source region and the p-type drain region, and containing silicon and oxygen, the first insulating layer having a first region;
a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, the second insulating layer having a second region, the second region being in a 0.3 nm range in a film thickness direction from a interface between the first insulating layer and the second insulating layer, the first region being in a 0.3 nm range in a film thickness direction from the interface between the first insulating layer and the second insulating layer, and each of the first and second regions including aluminum atoms with a concentration of 1×
1020 cm−
3 or more to 1×
1022 cm−
3 or less; and
a first gate electrode formed on the second insulating layer, and an n-channel MIS transistor including;
a p-type semiconductor region formed on the substrate and insulated from the n-type semiconductor region;
an n-type source region and an n-type drain region formed to face each other in the p-type semiconductor region;
a third insulating layer formed on the p-type semiconductor region between the n-type source region and n-type drain region, and containing silicon and oxygen;
a fourth insulating layer formed on the third insulating layer, and containing hafnium, silicon, oxygen, and nitrogen; and
a second gate electrode formed above the fourth insulating layer.
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Accused Products
Abstract
A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a substrate; a p-channel MIS transistor including; an n-type semiconductor region formed on the substrate; a p-type source region and a p-type drain region formed to face each other in the n-type semiconductor region; a first insulating layer formed on the n-type semiconductor region between the p-type source region and the p-type drain region, and containing silicon and oxygen, the first insulating layer having a first region; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, the second insulating layer having a second region, the second region being in a 0.3 nm range in a film thickness direction from a interface between the first insulating layer and the second insulating layer, the first region being in a 0.3 nm range in a film thickness direction from the interface between the first insulating layer and the second insulating layer, and each of the first and second regions including aluminum atoms with a concentration of 1×
1020 cm−
3 or more to 1×
1022 cm−
3 or less; anda first gate electrode formed on the second insulating layer, and an n-channel MIS transistor including; a p-type semiconductor region formed on the substrate and insulated from the n-type semiconductor region; an n-type source region and an n-type drain region formed to face each other in the p-type semiconductor region; a third insulating layer formed on the p-type semiconductor region between the n-type source region and n-type drain region, and containing silicon and oxygen; a fourth insulating layer formed on the third insulating layer, and containing hafnium, silicon, oxygen, and nitrogen; and a second gate electrode formed above the fourth insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a substrate; a p-channel MIS transistor including; an n-type semiconductor region formed on the substrate; a p-type source region and a p-type drain region formed to face each other in the n-type semiconductor region; a first insulating layer formed on the n-type semiconductor region between the p-type source region and the p-type drain region, and containing silicon and oxygen, the first insulating layer having a first region; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, the second insulating layer having second and third regions, the second region being in a 0.3 nm range in a film thickness direction from an interface between the first insulating layer and the second insulating layer, the first region being in a 0.3 nm range in a film thickness direction from the interface between the first insulating layer and the second insulating layer, and each of the first and second regions including aluminum atoms with a concentration of 1×
1020 cm−
3 or more to 1×
1022 cm−
3 or less;a third insulating layer formed on the second insulating layer, and containing aluminum and oxygen, the third insulating layer having a fourth region, the fourth region being in a 0.3 nm range in a film thickness direction from an interface between the second insulating layer and the third insulating layer, the third region being in a 0.3 nm range in a film thickness direction from the interface between the second insulating layer and the third insulating layer, and each of the third and fourth regions including aluminum atoms with a concentration of 1×
1022 cm−
3 or more to 3×
1022 cm−
3 or less; anda first gate electrode formed on the third insulating layer, and an n-channel MIS transistor including; a p-type semiconductor region formed on the substrate and insulated from the n-type semiconductor region; an n-type source region and an n-type drain region formed to face each other in the p-type semiconductor region; a fourth insulating layer formed on the p-type semiconductor region between the n-type source region and the n-type drain region, and containing silicon and oxygen; a fifth insulating layer formed on the fourth insulating layer, and containing hafnium, silicon, oxygen, and nitrogen; and a second gate electrode formed above the fifth insulating layer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor device comprising:
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a substrate; a p-channel MIS transistor including; an n-type semiconductor region formed on the substrate; a p-type source region and a p-type drain region formed to face each other in the n-type semiconductor region; a first insulating layer formed on the n-type semiconductor region between the p-type source region and the p-type drain region, and containing silicon and oxygen, the first insulating layer having a first region; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, the second insulating layer having a second and third regions, the second region being in a 0.3 nm range in a film thickness direction from a interface between the first insulating layer and the second insulating layer, the first region being in a 0.3 nm range in a film thickness direction from the interface between the first insulating layer and the second insulating layer, and each of the first and second regions including aluminum atoms with a concentration of 1×
1020 cm−
3 or more to 1×
1022 cm−
3 or less;a third insulating layer formed on the second insulating layer, and containing aluminum and oxygen, the third insulating layer having a fourth region, the fourth region being in a 0.3 nm range in a film thickness direction from an interface between the second insulating layer and the third insulating layer, the third region being in a 0.3 nm range in a film thickness direction from the interface between the second insulating layer and the third insulating layer, and each of the third and fourth regions including aluminum atoms with a concentration of 1×
1022 cm−
3 or more to 3×
1022 cm−
3 or less; anda first gate electrode formed on the third insulating layer, and an n-channel MIS transistor including; a p-type semiconductor region formed on the substrate and insulated from the n-type semiconductor region; an n-type source region and an n-type drain region formed to face each other in the p-type semiconductor region; a fourth insulating layer formed on the p-type semiconductor region between the n-type source region and the n-type drain region, and containing silicon and oxygen the fourth insulating layer having a fifth region; a fifth insulating layer formed on the fourth insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, the fifth insulating layer having a sixth and seventh regions, the sixth region being in a 0.3 nm range in a film thickness direction from an interface between the fourth insulating layer and the fifth insulating layer, the fifth region being in a 0.3 nm range in a film thickness direction from the interface between the fourth insulating layer and the fifth insulating layer, and each of the fifth and sixth regions including aluminum atoms with a concentration of 1×
1020 cm−
3 or more to 1×
1022 cm−
3 or less;a sixth insulating layer formed on the fifth insulating layer, and containing aluminum and oxygen, the sixth insulating layer having an eighth region, the eighth region being in a 0.3 nm range in a film thickness direction from an interface between the fifth insulating layer and the sixth insulating layer, the seventh region being in a 0.3 nm range in a film thickness direction from the interface between the fifth insulating layer and the sixth insulating layer, and each of the seventh and eighth regions including aluminum atoms with a concentration of 1×
1022 cm−
3 or more to 3×
1022 cm−
3 or less; anda second gate electrode formed above the sixth insulating layer. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsKoyama, Masato, Sekine, Katsuyuki, Ichihara, Reika, Tsuchiya, Yoshinori, Kamimuta, Yuuichi
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Primary Examiner(s)Gurley; Lynne A
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Assistant Examiner(s)YUSHINA, GALINA G
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Application NumberUS11/753,186Publication NumberTime in Patent Office1,230 DaysField of Search257/369, 257/371, 257/372, 257/E27.068, 257/E21.047, 257/24, 257/204, 257/411, 257/E21.19, 257/406, 257/410, 257/E27.108, 257/407, 438/231, 438/197US Class Current257/24CPC Class CodesH01L 21/28097 the final conductor layer n...H01L 21/823842 gate conductors with differ...H01L 21/823857 with a particular manufactu...H01L 27/092 complementary MIS field-eff...H01L 29/4975 being a silicide layer, e.g...H01L 29/513 the variation being perpend...H01L 29/517 the insulating material com...H01L 29/7833 with lightly doped drain or...
