Silicon carbide semiconductor device

• US 7,808,003 B2
• Filed: 10/02/2008
• Issued: 10/05/2010
• Est. Priority Date: 10/05/2007
• Status: Expired due to Fees

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Endo, Takeshi, Okuno, Eiichi
• Primary Examiner(s): Soward; Ida M
• Application Number:
  US12/285,351
• Publication Number:
  US 20090090920A1
• Time in Patent Office: 733 Days
• Field of Search: 257/77, 257/E21.603, 257/E21.605, 257/E29.297, 257/E29.298
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A silicon carbide semiconductor device is disclosed. The silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type and located on a first surface of the substrate; and a vertical type semiconductor element. The vertical type semiconductor element includes: an impurity layer having a second conductivity type, and located in a surface portion of the drift layer; and a first conductivity type region located in the drift layer, spaced away from the impurity layer, located closer to the substrate than the impurity layer, and having an impurity concentration higher than the drift layer.

Claims

1. A silicon carbide semiconductor device having a vertical type semiconductor element, comprising:

a substrate made of silicon carbide;

a drift layer made of silicon carbide, having a first conductivity type, and located on a first surface of the substrate, wherein the substrate and the drift layer has a cell portion;

an impurity layer having a second conductivity type, located in the cell portion, and located in a surface portion of the drift layer;

a first electrode located on a first surface side of the substrate so that the impurity layer and the drift layer are located between the first electrode and the substrate;

a second electrode located on a second surface side of the substrate; and

a first conductivity type region located in the cell portion, located in the drift layer, spaced away from the impurity layer, located closer to the substrate than the impurity layer, and having an impurity concentration larger than the drift layer,

wherein the vertical type semiconductor device element is configured so that a current flows between the first electrode and the second electrode.

2. The silicon carbide semiconductor device according to claim 1, wherein

the first conductivity type region includes a plurality of first conductivity type region parts arranged in a direction substantially parallel to the first surface of the substrate.

3. The silicon carbide semiconductor device according to claim 1, wherein

the first conductivity type region is in contact with the substrate.

4. A silicon carbide semiconductor device having an accumulation type MOS structure semiconductor element, comprising:

a substrate made of silicon carbide, and having one of a first conductivity type and a second conductivity type;

a drift layer made of silicon carbide, having the first conductivity type, and located above the substrate, wherein the substrate and the drift layer provide a cell portion;

a base region made of silicon carbide, having the second conductivity type, located in the cell portion, and located in a surface portion of the drift layer;

a channel region made of silicon carbide, having the first conductivity type, and located on a surface of the base region and a surface of the drift layer;

a source region made of silicon carbide, having the first conductivity type, extending from the channel region into the base region, and having an impurity concentration larger than the drift layer;

a gate insulation film located on a surface of the channel region;

a gate electrode located above the gate insulation film;

a source electrode electrically connected with the source region;

a drain electrode located on a rear surface side of the substrate; and

a first conductivity type region located in the cell portion, located in drift layer, spaced away from the base region, located closer to the substrate than the base region, and having an impurity concentration larger than the drift layer,

wherein the accumulation type semiconductor element is configured so that a current flow between the source electrode and the drain electrode through the source region and the drift layer under control of channel formation in the channel region, the channel formation being controlled by controlling a voltage applied to the gate electrode.

5. The silicon carbide semiconductor device according to claim 4, further comprising:

a trench located in the drift layer, wherein;

the gate electrode is located in the trench through the gate insulation film; and

that the source region and the channel region contact a side wall of the trench, so that the current flows through a portion of the channel region.

6. A silicon carbide semiconductor device having an inversion type MOS structure semiconductor element, the device comprising:

a substrate made of silicon carbide, and having one of a first conductivity type and a second conductivity type;

a drift layer made of silicon carbide, having the first conductivity type, and located above the substrate, wherein the substrate and the drift layer provide a cell portion;

a base region made of silicon carbide, having the second conductivity type, located in the cell portion, and located in a surface portion of the drift layer;

a source region made of silicon carbide, having the first conductivity type, located in the base region, and having an impurity concentration larger than the drift layer;

a gate insulation film located on a surface of the base region;

a gate electrode located above the gate insulation film;

a source electrode electrically connected with the source region;

a drain electrode located on a rear surface side of the substrate; and

a first conductivity type region located in the cell portion, located in drift layer, spaced away from the base region, located closer to the substrate than the base region, having an impurity concentration larger than the drift layer,

wherein the inversion type semiconductor element is configured so that a current flow between the source electrode and the drain electrode through the source region and the drift layer under control of a channel formed in a portion of the base region, the portion contacting the gate electrode, the channel being controlled by a voltage applied to the gate electrode.

7. The silicon carbide semiconductor device according to claim 6, further comprising:

a trench located in the drift layer, wherein;

the gate electrode is located in the trench through the gate insulation film; and

the source region and the base region contact a side wall of the trench, so that the current flows through a portion of the base region contacting the side wall of the trench.

8. The silicon carbide semiconductor device according to claim 6, further comprising:

a contact region for electrically connecting the source electrode and the base region, wherein;

the contact region is located opposite to the channel region with respect to the source region; and

the first conductivity type region is located below the contact region and space away from the base region.

9. The silicon carbide semiconductor device according to claim 6, wherein

the first conductivity type region is located below the source region and spaced away from the base region.

10. The silicon carbide semiconductor device according to claim 6, wherein

the first conductivity type region is located below the trench and spaced away from the trench.

11. The silicon carbide semiconductor device according to claim 6, wherein:

the first conductivity type region includes a plurality of first conductivity type region parts arranged in a direction parallel to a top surface of the substrate.

12. The silicon carbide semiconductor device according to claim 6, wherein:

the first conductivity type region contacts the substrate.

13. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, having a first conductivity type, and having a principal surface and a rear surface;

a drift layer made of silicon carbide, having the first conductivity type, located above the principal surface of the substrate, and having an impurity concentration smaller than the substrate, wherein the substrate and the drift layer provide a cell portion; and

a Schottky barrier diode located in the cell portion, wherein the Schottky barrier diode includes;

a Schottky electrode having a Schottky contact with the drift layer;

an ohmic electrode located on the rear surface of the substrate; and

a first conductivity type region located in the drift layer, spaced away from the Schottky electrode, and having an impurity concentration larger than the drift layer.

14. The silicon carbide semiconductor device according to claim 13, further comprising:

a termination structure located in a periphery of the cell portion, wherein;

the termination structure includes a second conductivity type region;

the second conductivity type region is located in a surface portion of the drift layer so as to surround the cell portion; and

the first conductivity type region is located deeper than the second conductivity type region.

15. The silicon carbide semiconductor device according to claim 13, further comprising:

a junction barrier diode including a plurality of second conductivity type layers, wherein;

each second conductivity type layer is located below a part of the Schottky electrode, the part being in contact with the drift layer;

each second conductivity type layer is in contact with the Schottky electrode at a surface of the drift layer;

the plurality of second conductivity type layers are spaced away from each other; and

the first conductivity type region is located in the drift layer, located deeper than the plurality of second conductivity type layers, and spaced away from the plurality of second conductivity type layers.

16. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, having a first conductivity type, and having a principal surface and a rear surface;

a drift layer made of silicon carbide, having the first conductivity type, located on the principal surface of the substrate, and having an impurity concentration smaller than the substrate, wherein the substrate and the drift layer provide a cell portion;

an insulation film located above the drift layer and having an opening located in the cell portion;

a second conductivity type layer located in the cell portion, and located in a surface portion of the drift layer; and

a P-N diode located in the cell portion and including;

a first ohmic electrode contacting the second conductivity type layer with an ohmic contact through the opening of the insulation film;

a second ohmic electrode located on a rear surface of the substrate; and

a first conductivity type region located in the cell portion, located in the drift layer, located deeper than the second conductivity type layer, having an impurity concentration larger than the drift layer.

17. The silicon carbide semiconductor device according to claim 16, further comprising:

a termination structure located in a periphery of the cell portion and including a second conductivity type region, wherein;

the second conductivity type region is located in a surface portion of the drift layer so as to surround the cell portion; and

the first conductivity type region is located deeper than the second conductivity type region.

18. The silicon carbide semiconductor device according to claim 16, wherein

the impurity concentration of the first conductivity type region is greater than or equal to 1×

10¹⁷ cm<sup>−

3</sup>.