Method of making three dimensional NAND memory

• US 7,808,038 B2
• Filed: 03/27/2007
• Issued: 10/05/2010
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Scheuerlein, Roy
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): Ligai; Maria
• Application Number:
  US11/691,858
• Publication Number:
  US 20080237698A1
• Time in Patent Office: 1,288 Days
• Field of Search: 257/67, 257/325, 257/326, 257/391, 257/E29.13, 257/E29.131, 257/E29.134, 257/328, 257/E29.262, 257/302, 438/268
• US Class Current: 257/328
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.

Claims

1. A monolithic, three dimensional NAND string, comprising a first memory cell located over a second memory cell, wherein:

a semiconductor active region of the first memory cell comprises a first pillar having a square or rectangular cross section when viewed from above, the first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

a semiconductor active region of the second memory cell comprises a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions; and

one second conductivity type semiconductor region in the first pillar directly physically contacts one second conductivity type semiconductor region in the second pillar.

2. The NAND string of claim 1, further comprising a select transistor located below the second memory cell.

3. The NAND string of claim 2, wherein:

the NAND string is formed vertically over a substrate;

the select transistor is located on the substrate or in a trench in the substrate;

the first memory cell is located in a first device level; and

the second memory cell is located in a second device level located on the select transistor and below the first device level.

4. The NAND string of claim 2, wherein:

the semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell;

the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor;

a first charge storage dielectric is located between the semiconductor active region of the first memory cell and a first word line; and

a second charge storage dielectric is located between the semiconductor active region of the second memory cell and a second word line.

5. The NAND string of claim 2, wherein:

the semiconductor active region of the select transistor comprises a third pillar; and

the second pillar is not aligned with the third pillar, such that the second pillar extends laterally past the third pillar.

6. The NAND string of claim 2, further comprising:

a bit line;

a source line; and

a select gate line of the select transistor.

7. A monolithic, three dimensional NAND string, comprising a first memory cell located over a second memory cell, wherein:

a semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

a semiconductor active region of the second memory cell comprises a second pillar located under the first pillar, the second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

one second conductivity type semiconductor region in the first pillar directly physically contacts one second conductivity type semiconductor region in the second pillar; and

at least one of the semiconductor active region of the second memory cell or a semiconductor active region of a select transistor is located in a trench in a substrate.

8. The NAND string of claim 7, further comprising the select transistor comprising the semiconductor active region located in the trench in the substrate.

9. The NAND string of claim 8, wherein:

the NAND string is formed vertically over the substrate;

the select transistor is located on the substrate or in a trench in the substrate;

the first memory cell is located in a first device level; and

the second memory cell is located in a second device level located on the select transistor and below the first device level.

10. The NAND string of claim 9, wherein:

the semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell;

the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor;

a first charge storage dielectric is located between the semiconductor active region of the first memory cell and a first word line; and

a second charge storage dielectric is located between the semiconductor active region of the second memory cell and a second word line.

11. The NAND string of claim 8, wherein:

the semiconductor active region of the select transistor comprises a third pillar; and

the second pillar is not aligned with the third pillar, such that the second pillar extends laterally past the third pillar.

12. The NAND string of claim 7, wherein the semiconductor active region of the second memory cell is located in the trench in the substrate.

13. A monolithic, three dimensional NAND string, comprising a first memory cell located over a second memory cell, wherein:

a semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

a semiconductor active region of the second memory cell comprises a second pillar located under the first pillar, the second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

one second conductivity type semiconductor region in the first pillar directly physically contacts one second conductivity type semiconductor region in the second pillar; and

the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar.

14. The NAND string of claim 13, further comprising a select transistor located below the second memory cell.

15. The NAND string of claim 14, wherein:

the semiconductor active region of the select transistor comprises a third pillar; and

the second pillar is not aligned with the third pillar, such that the second pillar extends laterally past the third pillar.

16. The NAND string of claim 14, wherein:

the NAND string is formed vertically over a substrate;

the select transistor is located on a substrate or in a trench in the substrate;

the first memory cell is located in a first device level; and

the second memory cell is located in a second device level located on the select transistor and below the first device level.

17. The NAND string of claim 16, wherein:

the semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell;

the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor;

a first charge storage dielectric is located between the semiconductor active region of the first memory cell and a first word line; and

a second charge storage dielectric is located between the semiconductor active region of the second memory cell and a second word line.

18. The NAND string of claim 17, wherein:

the first word line extends in a first direction; and

the second word line extends in a second direction different from the first direction.

19. The NAND string of claim 17, further comprising:

a bit line;

a source line; and

a select gate line of the select transistor.

20. The NAND string of claim 19, wherein:

the first and the second word lines extend perpendicular to the bit line; and

the first and the second word lines extend parallel to at least one of the source line and the select gate line.