Standard cell without OD space effect in Y-direction

• US 7,808,051 B2
• Filed: 12/29/2008
• Issued: 10/05/2010
• Est. Priority Date: 09/29/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shu-Min, Li, Ping Chung, Hou, Yung-Chin, Lu, Lee-Chung, Tai, Chun-Hui, Tien, Li-Chun, Guo, Ta-Pen
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US12/345,372
• Publication Number:
  US 20100078725A1
• Time in Patent Office: 645 Days
• Field of Search: 257/69, 257/204, 257/206, 257/296, 257/368, 257/E27.06, 257/E27.108, 257/E29.02
• US Class Current: 257/368
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate;

a first active region in the semiconductor substrate;

a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region;

a gate electrode strip over the first and the second active regions and forming a first MOS device and a second MOS device with the first active region and the second active region, respectively;

a first spacer bar in the semiconductor substrate and connected to the first active region, wherein at least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region; and

a second spacer bar in the semiconductor substrate and connected to the second active region, wherein at least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

2. The integrated circuit structure of claim 1, wherein the first spacer bar, the second spacer bar, the first MOS device, and the second MOS device are within boundaries of a standard cell.

3. The integrated circuit structure of claim 2, wherein each of the first spacer bar and the second spacer bar adjoins three boundaries of the standard cell.

4. The integrated circuit structure of claim 1, wherein the first spacer bar and the first active region are both of a first conductivity type.

5. The integrated circuit structure of claim 4, wherein the second spacer bar and the second active region are both of a second conductivity type opposite the first conductivity type.

6. The integrated circuit structure of claim 5 further comprising:

a third active region in the semiconductor substrate and of a same conductivity type as the first spacer bar and the first active region; and

a fourth active region in the semiconductor substrate and of a same conductivity type as the second spacer bar and the second active region, wherein the third active region is between and adjoining the first spacer bar and the first active region, and the fourth active region is between and adjoining the second spacer bar and the second active region.

7. The integrated circuit structure of claim 1, wherein the first active region and the first spacer bar are fully separated from each other by a first shallow trench isolation (STI) region, and wherein the second active region and the second spacer bar are fully separated from each other by a second STI region.

8. The integrated circuit structure of claim 1 further comprising a tap cell comprising a pickup region for a well region, wherein the first active region is in the well region, and wherein the tap cell further comprises a third spacer bar adjoining, and of a same conductivity type as, the first spacer bar.

9. The integrated circuit structure of claim 1 further comprising a filler cell comprising a dummy gate electrode strip and a dummy active region, wherein the filler cell further comprises a third spacer bar adjoining, and of a same conductivity type as, the first spacer bar.

10. An integrated circuit structure comprising:

a semiconductor substrate;

a first active region in the semiconductor substrate;

a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region;

a gate electrode strip over the first and the second active regions and forming a first MOS device and a second MOS device with the first active region and the second active region, respectively;

a first spacer bar in the semiconductor substrate and of a same conductivity type as the first active region, wherein the first spacer bar is an active region adjacent to and disconnected from the first active region; and

a second spacer bar in the semiconductor substrate and of a same conductivity type as the second active region, wherein the second spacer bar is an additional active region adjacent to and disconnected from the second active region.

11. The integrated circuit structure of claim 10, wherein the first spacer bar, the second spacer bar, the first MOS device, and the second MOS device are within boundaries of a standard cell.

12. The integrated circuit structure of claim 11, wherein each of the first spacer bar and the second spacer bar adjoins three boundaries of the standard cell.

13. The integrated circuit structure of claim 10 further comprising a first shallow trench isolation (STI) region between and adjoining the first active region and the first spacer bar, and a second STI region between and adjoining the second active region and the second spacer bar.

14. The integrated circuit structure of claim 10 further comprising a tap cell comprising a pickup region for a well region, wherein the first active region is in the well region, and wherein the tap cell further comprises a third spacer bar adjoining, and of a same conductivity type as, the first spacer bar.

15. The integrated circuit structure of claim 10 further comprising a filler cell comprising a dummy gate electrode strip and a dummy active region, wherein the filler cell further comprises a third spacer bar adjoining, and of a same conductivity type as, the first spacer bar.

16. An integrated circuit structure comprising:

a standard cell comprising a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary and the second boundary are on opposite ends of the standard cell, and the third boundary and the fourth boundary are on opposite ends of the standard cell, and wherein the standard cell comprises;

a semiconductor substrate;

a first active region in the semiconductor substrate;

a gate electrode strip over the first active region;

a first spacer bar being an additional active region in the semiconductor substrate, wherein the first spacer bar adjoins an entirety of the third boundary, a portion of the first boundary, and a portion of the second boundary, and wherein the first spacer bar and the first active region are of a first conductivity type; and

a first insulation region in the semiconductor substrate, wherein the first insulation region is between and adjoining at least a portion of the first active region and at least a portion of the first spacer bar.

17. The integrated circuit structure of claim 16 further comprising:

a second spacer bar in the semiconductor substrate, wherein the second spacer bar adjoins an entirety of the fourth boundary, a portion of the first boundary, and a portion of the second boundary, and wherein the second spacer bar and a second active region are of a second conductivity type opposite the first conductivity type; and

a second insulation region in the semiconductor substrate, wherein the second insulation region is between and adjoining at least a portion of the second active region and at least a portion of the second spacer bar.

18. The integrated circuit structure of claim 16 further comprising a silicide region over and adjoining the first spacer bar.

19. The integrated circuit structure of claim 16 further comprising a tap cell comprising a second spacer bar adjoining, and forming a straight spacer bar with, the first spacer bar.

20. The integrated circuit structure of claim 16 further comprising a filler cell comprising:

a dummy gate electrode strip;

a dummy active region; and

a second spacer bar adjoining, and forming a straight spacer bar with, the first spacer bar.

21. The integrated circuit structure of claim 16 further comprising:

a second active region in the semiconductor substrate and of a same conductivity type as the first spacer bar and the first active region, wherein the second active region is between and adjoining a portion of the first spacer bar and a portion of the first active region.