Method, apparatus, and system for flash memory

• US 7,808,053 B2
• Filed: 12/29/2006
• Issued: 10/05/2010
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Tran, Luan C., Haller, Gordon
• Primary Examiner(s): Cao; Phat X
• Application Number:
  US11/618,658
• Publication Number:
  US 20080162781A1
• Time in Patent Office: 1,376 Days
• Field of Search: 257/390
• US Class Current: 257/390
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells

Abstract

Embodiments of the present invention provide apparatus, methods and systems that include a substrate including a central region and a peripheral region; a plurality of layers above a surface of the substrate, a first plurality of pitch-multiplied spacers on a top surface of the plurality of layer, the first plurality of pitch-multiplied spacers being above the central region of the substrate, and a second plurality of pitch-multiplied spacers on the top surface of the plurality of layers, the second plurality of pitch-multiplied spacers above the peripheral region and including at least one pitch-multiplied spacer having a surface at a distance from the at least one pitch multiplied spacer having a surface at the boundary.

Claims

1. An apparatus comprising:

a substrate including a central region and a peripheral region;

a plurality of layers above a surface of the substrate, the plurality of layers covering at least a portion of the central region and at least a portion of the peripheral region adjacent to the portion of the central region covered by the plurality of layers, the plurality of layers including a mask layer overlaying the substrate and a hard mask layer overlaying the mask layer, the hard mask layer having a hard mask layer top surface;

a first plurality of pitch-multiplied oxide spacers on the hard mask layer top surface, the first plurality of pitch-multiplied oxide spacers being above the central region of the substrate and including at least one pitch-multiplied oxide spacer having a substantially flat surface at a boundary between the central region and the peripheral region and a curved surface extending from the hard mask layer top surface up to the substantially flat surface; and

a second plurality of pitch-multiplied oxide spacers on the hard mask layer top surface, the second plurality of pitch-multiplied oxide spacers above the peripheral region and including at least one pitch-multiplied oxide spacer having a substantially flat surface at a distance from the at least one pitch multiplied oxide spacer having the substantially flat surface at the boundary, the distance no less than a width at the hard mask layer top surface between two of the plurality of pitch-multiplied oxide spacers above the central region, and no more than a width at the hard mask layer top surface of a second mask above an interconnect in the peripheral region and adjacent to the boundary.

2. The apparatus of claim 1, wherein the at least one pitch-multiplied oxide spacer having the substantially flat surface at the boundary between the central region and the peripheral region is above an area of the substrate forming an interconnect in the central region.

3. The apparatus of claim 1, wherein the first plurality of pitch-multiplied oxide spacers and the second plurality of pitch-multiplied oxide spacers include silicon oxide.

4. The apparatus of claim 1, wherein each of the first plurality of pitch-multiplied oxide spacers is above an area of the central region to be used as an interconnect line in an array of memory cells.

5. The apparatus of claim 4, wherein the array of memory cells includes NAND flash memory cells.

6. A system comprising:

a processor;

a memory device coupled to the processor, the memory device including a substrate including a central region and a peripheral region and a plurality of layers above a surface of the substrate;

the plurality of layers above the surface of the substrate covering at least a portion of the central region and at least a portion of the peripheral region adjacent to the portion of the central region covered by the plurality of layers;

the memory device formed using a first plurality of pitch-multiplied spacers on a top surface of the plurality of layers, the first plurality of pitch-multiplied spacers being above the central region of the substrate and including at least one pitch-multiplied spacer having a first substantially flat surface at a boundary between the central region and the peripheral region and a first curved surface extending from the top surface up to the first substantially flat surface; and

the memory device further formed using a second plurality of pitch-multiplied spacers on the top surface of the plurality of layers, the second plurality of pitch-multiplied spacers above the peripheral region and including at least one pitch-multiplied spacer having a second substantially flat surface at a distance from the at least one pitch multiplied spacer having the first sustainably flat surface at the boundary and including a second curved surface extending from the top surface up to the second substantially flat surface, the distance no less than a width at the top surface between two of the plurality of pitch-multiplied spacers above the central region, and no more than a width at the top surface of a mask above the top surface and above an interconnect in the peripheral region and adjacent to the boundary.

7. The system of claim 6, wherein the memory device includes NAND flash memory devices.

8. The system of claim 6, wherein the processor is coupled to a network.

9. The system of claim 6, wherein the first plurality of pitch-multiplied spacers and the second plurality of pitch-multiplied spacers include silicon oxide.

10. The system of claim 6, the memory device includes a programmable logic array including a plurality of NOR flash memory cells.