Semiconductor package with half-etched locking features

• US 7,808,084 B1
• Filed: 05/06/2008
• Issued: 10/05/2010
• Est. Priority Date: 05/06/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Lee, Chang Deok, Na, Do Hyun
• Primary Examiner(s): Tran; Thien F
• Application Number:
  US12/116,127
• Time in Patent Office: 882 Days
• Field of Search: 257/666, 257/670, 257/676, 257/784, 257/787, 257/E23.031
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Disclosed is a lead frame, a semiconductor device and a fabrication method related to the semiconductor device. Since the lead frame has a land connecting bar, an upper surface of which is half-etched, the land connecting bar is more easily removed by a blade than a conventional land connecting bar in a fabrication process for the semiconductor device. Accordingly, stress applied to the lands when the land connecting bar is removed is reduced, and a flatness of the lands is maintained. Also, first and second lands constituting the lands are alternately formed with the land connecting bar, leads are alternately formed with the second lands, and wire bonding regions of the leads are positioned on a plane higher than the second lands. Accordingly, an interval between the conductive wires can be constantly maintained and the conductive wires have different traces, thus preventing a short between the conductive wires due to wire sweeping in an encapsulation process.

Claims

1. A semiconductor device comprising:

a lead frame including;

a die pad;

a plurality of first lands arranged to extend at least partially about the die pad;

a plurality of second lands arranged to extend at least partially about the die pad such that the first lands are disposed between the die pad and the second lands, each of the second lands being offset relative to a respective one of the first lands; and

a plurality of leads which each include a first portion and a second portion, the leads being arranged to extend at least partially about the die pad such that the first and second lands are disposed between the die pad and the first portions, each of the first portions being offset relative to a respective one of the second lands and generally aligned with a respective one of the first lands;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first and second lands and the leads; and

an encapsulant for encapsulating the lead frame and the semiconductor die such that portions of the second portions of the leads protrude from a side portion of the encapsulant and the first and second lands are each exposed in a lower surface of the encapsulant.

2. The semiconductor device of claim 1 wherein the semiconductor die is electrically connected to at least one of each of the first and second lands and the leads by conductive wires which are covered by the encapsulant.

3. The semiconductor device of claim 2 wherein the first portions of at least some of the leads each include a downset formed therein and covered by the encapsulant.

4. The semiconductor device of claim 3 wherein the first portions of the leads including a downset further define of wire bonding zone which is disposed between the downset and the die pad.

5. The semiconductor device of claim 4 wherein the die pad and the first and second lands extend along a first plane, and the wire bond zones of the first portions of the leads extend along a second plane which is disposed in spaced, generally parallel relation to the first plane.

6. The semiconductor device of claim 5 wherein the second portions of the leads extend along a third plane which is disposed in spaced, generally parallel relation to the second plane such that second plane extends between the first and third planes.

7. The semiconductor device of claim 1 wherein:

each of the first lands includes a locking projection which is covered by the encapsulant; and

each of the seconds lands includes a locking projection which is covered by the encapsulant.

8. The semiconductor device of claim 7 wherein:

each of the first lands defines a lower surface, and the locking projection of each of the first lands is defined by a half-etched portion formed within the lower surface thereof; and

each of the second lands defines a lower surface, and the locking projection of each of the second lands is defined by a half-etched portion formed within the lower surface thereof.

9. The semiconductor device of claim 8 wherein:

each of the first lands includes an end portion, with the locking projection of each of the first lands being disposed within the end portion thereof; and

each of the second lands includes an end portion, with the locking projection of each of the second lands being disposed within the end portion thereof.

10. The semiconductor device of claim 1 wherein the die pad has a generally quadrangular configuration, and the first and second lands, and the leads are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die pad.

11. The semiconductor device of claim 1 wherein the portions of the second portions of the leads which protrude from the side portion of the encapsulant are bent to assume a gull-wing configuration.

12. A semiconductor device comprising:

a die pad;

a plurality of first lands arranged to extend at least partially about the die pad;

a plurality of second lands arranged to extend at least partially about the die pad such that the first lands are disposed between the die pad and the second lands;

a plurality of leads which each include a first portion and a second portion, at least some of the first portions of at least some of the leads each including a downset formed therein, the leads being arranged to extend at least partially about the die pad such that the first and second lands are disposed between the die pad and the first portions of the leads;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first and second lands and the leads; and

an encapsulant for encapsulating the lead frame and the semiconductor die such that portions of the second portions of the leads protrude from a side portion of the encapsulant, each downset is covered by the encapsulant, and the first and second lands are each exposed in a lower surface of the encapsulant.

13. The semiconductor device of claim 12 wherein the semiconductor die is electrically connected to at least one of each of the first and second lands and the leads by conductive wires which are covered by the encapsulant.

14. The semiconductor device of claim 13 wherein the first portions of the leads including a downset further define of wire bonding zone which is disposed between the downset and the die pad.

15. The semiconductor device of claim 14 wherein the die pad and the first and second lands extend along a first plane, the wire bond zones of the first portions of the leads extend along a second plane which is disposed in spaced, generally parallel relation to the first plane, and the second portions of the leads extend along a third plane which is disposed in spaced, generally parallel relation to the second plane such that second plane extends between the first and third planes.

16. The semiconductor device of claim 12 wherein the portions of the second portions of the leads which protrude from the side portion of the encapsulant are bent to assume a gull-wing configuration.

17. The semiconductor device of claim 12 wherein:

each of the first lands includes a locking projection which is covered by the encapsulant; and

each of the seconds lands includes a locking projection which is covered by the encapsulant.

18. The semiconductor device of claim 17 wherein:

each of the first lands includes a lower surface and an end portion, and the locking projection of each of the first lands is defined by a half-etched portion formed within the lower surface at the end portion thereof; and

each of the second lands includes a lower surface and an end portion, and the locking projection of each of the second lands is defined by a half-etched portion formed within the lower surface at the end portion thereof.

19. A semiconductor device comprising:

a die pad;

a plurality of first lands disposed in spaced relation to the die pad;

a plurality of second lands disposed in spaced relation to and offset relative to respective ones of the first lands; and

a plurality of leads which each include a first portion and a second portion, the first portions of the leads being disposed in spaced relation to and offset relative to respective ones of the second lands and generally aligned with respective ones of the first lands;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first and second lands and the leads; and

an encapsulant for encapsulating the lead frame and the semiconductor die such that portions of the second portions of the leads protrude from a side portion of the encapsulant and the first and second lands are each exposed in a lower surface of the encapsulant.

20. A semiconductor device comprising:

a die pad;

a plurality of first lands arranged to extend at least partially about the die pad, each of the first lands including a locking projection;

a plurality of second lands arranged to extend at least partially about the die pad such that the first lands are disposed between the die pad and the second lands, each of the second lands including a locking projection;

a plurality of leads which each include a first portion and a second portion, the leads being arranged to extend at least partially about the die pad such that the first and second lands are disposed between the die pad and the first portions of the leads;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first and second lands and the leads; and

an encapsulant for encapsulating the lead frame and the semiconductor die such that portions of the second portions of the leads protrude from a side portion of the encapsulant, the locking projections of the first and second lands are covered by the encapsulant, and the first and second lands are each exposed in a lower surface of the encapsulant.

21. The semiconductor device of claim 20 wherein:

each of the first lands includes a lower surface and an end portion, and the locking projection of each of the first lands is defined by a half-etched portion formed within the lower surface at the end portion thereof; and

each of the second lands includes a lower surface and an end portion, and the locking projection of each of the second lands is defined by a half-etched portion formed within the lower surface at the end portion thereof.