Semiconductor integrated circuit device

• US 7,808,107 B2
• Filed: 05/08/2009
• Issued: 10/05/2010
• Est. Priority Date: 12/18/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Inventors: Shinozaki, Masao, Akioka, Takashi, Asari, Sanae, Kohara, Yutaka, Miyata, Shusaku, Nishimoto, Kenji, Nakazato, Shinji
• Primary Examiner(s): Menz; Douglas M
• Application Number:
  US12/453,383
• Publication Number:
  US 20090219069A1
• Time in Patent Office: 515 Days
• Field of Search: 257/759, 257/758
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/06 : Polymers polymers per se C08; polymer adhesives C09J
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

Claims

1. A semiconductor integrated circuit device comprising:

a semiconductor substrate;

circuit elements and wirings which are provided on one main surface of the semiconductor substrate and constitute a semiconductor integrated circuit;

a first pad electrode and a second pad electrode provided over the one main surface and electrically connected to the circuit;

a protective film provided over the circuit except for openings over surfaces of the first and second pad electrodes;

an organic insulating film provided over the protective film except for the openings; and

a first conductive layer provided over the organic insulating film and providing a direct electrical connection from the first pad electrode to the second pad electrode.

2. The semiconductor integrated circuit device according to claim 1, wherein the conductive layer is a rewiring.

3. The semiconductor integrated circuit device according to claim 1, further comprising:

a third pad electrode provided over the one main surface; and

a second conductive layer, for electrically connecting to an external terminal, provided over the organic insulating film and electrically connected to the third pad electrode.

4. The semiconductor integrated circuit device according to claim 3, wherein the external terminal is a bump electrode.

5. The semiconductor integrated circuit device according to claim 1, wherein the first pad electrode and the second pad electrode are respectively bonding pads.

6. The semiconductor integrated circuit device according to claim 3, wherein the first and second pad electrodes are respectively set larger than the external terminal in area.

7. The semiconductor integrated circuit device according to claim 1, wherein the second pad electrode is electrically connect to the third pad electrode.

8. The semiconductor integrated circuit device according to claim 1, wherein the first conductive layer does not directly contact with an external terminal.

9. The semiconductor integrated circuit device according to claim 1, wherein the protective film includes a silicon nitride film.

10. The semiconductor integrated circuit device according to claim 1, wherein the second conductive layer includes a copper film having a thickness greater than a thickness of the first and second pad electrodes.

11. A semiconductor integrated circuit device comprising:

a semiconductor substrate;

circuit elements and wirings which are provided on one main surface of the semiconductor substrate and constitute a semiconductor integrated circuit;

a first insulating film provided over the circuit elements and the wirings;

a first pad electrode and a second pad electrode provided over the first insulating film and electrically connected to the circuit;

a protective film provided over the circuit except for openings over surfaces of the first and second pad electrodes;

a second insulating film provided over the protective film except for the openings; and

a first conductive layer provided over the second insulating film and providing a direct electrical connection from the first pad electrode to the second pad electrode.

12. The semiconductor integrated circuit device according to claim 11, further comprising:

a third pad electrode provided over the first insulating film; and

a second conductive layer, for electrically connecting to an external terminal, provided over the second insulating film and electrically connected to the third pad electrode.

13. The semiconductor integrated circuit device according to claim 12, wherein the external terminal is a bump electrode.

14. The semiconductor integrated circuit device according to claim 11, wherein the first pad electrode and the second pad electrode are respectively bonding pads.

15. The semiconductor integrated circuit device according to claim 12,

wherein the first and second pad electrodes are respectively set larger than the external terminal in area.

16. The semiconductor integrated circuit device according to claim 11, wherein the second pad electrode is electrically connect to the third pad electrode.

17. The semiconductor integrated circuit device according to claim 11, wherein the first conductive layer does not directly contact with an external terminal.

18. The semiconductor integrated circuit device according to claim 11, wherein the protective film includes a silicon nitride film.

28. The semiconductor integrated circuit device according to claim 11, wherein the second conductive layer includes a copper film having a thickness greater than a thickness of the first and second pad electrodes.

19. A semiconductor integrated circuit device comprising:

a semiconductor substrate;

circuit elements and wirings which are provided on one main surface of the semiconductor substrate and constitute a semiconductor integrated circuit;

a first insulating film provided over the circuit elements and the wirings;

a first pad electrode and a second pad electrode provided over the first insulating film and electrically connected to the circuit;

a protective film provided over the circuit except for openings over surfaces of the first and second pad electrodes; and

a first conductive layer provided over the protective film and providing a direct electrical connection from the first pad electrode to the second pad electrode.

20. The semiconductor integrated circuit device according to claim 19, further comprising:

a third pad electrode provided over the first insulating film; and

a second conductive layer, for electrically connecting to an external terminal, provided over the protective film and electrically connected to the third pad electrode.

21. The semiconductor integrated circuit device according to claim 20, wherein external terminal is a bump electrode.

22. The semiconductor integrated circuit device according to claim 19, wherein the first pad electrode and the second pad electrode are respectively bonding pads.

23. The semiconductor integrated circuit device according to claim 20, wherein the first and second pad electrodes are respectively set larger than the external terminal in area.

24. The semiconductor integrated circuit device according to claim 19, wherein the second pad electrode is electrically connect to the third pad electrode.

25. The semiconductor integrated circuit device according to claim 19, wherein the first conductive layer does not directly contact with an external terminal.

26. The semiconductor integrated circuit device according to claim 19, wherein the protective film includes a silicon nitride film.

27. The semiconductor integrated circuit device according to claim 19, wherein the second conductive layer includes a copper film having a thickness greater than a thickness of the first and second pad electrodes.