Processed wafer via

• US 7,808,111 B2
• Filed: 11/06/2006
• Issued: 10/05/2010
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): Warren; Matthew E
• Application Number:
  US11/556,747
• Publication Number:
  US 20070197013A1
• Time in Patent Office: 1,429 Days
• Field of Search: 257/621, 257/698, 257/773, 257/774, 257/E23.011, 257/E23.145, 257/E23.174, 257/777
• US Class Current: 257/774
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0615 : Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/13012 : in top view
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8121 : using a reflow oven
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/427 : Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 428/24174 : including sheet or component perpendicular to plane of web or sheet

Abstract

An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.

Claims

1. An apparatus comprising:

a back-end processed semiconductor wafer including a substrate and a metallization layer;

a via extending from an outer surface of the substrate to the metallization layer; and

an electrically-conductive material provided within the via, wherein the electrically-conductive material forms an electrically-conductive path between the outer surface of the substrate and the metallization layer;

wherein the back-end processed semiconductor wafer is coupled to a front-end processed semiconductor wafer to form a hybridized electronic chip, wherein the back-end processed semiconductor wafer has not been front-end processed and the front-end processed semiconductor wafer has not been back-end processed, and wherein the via of the back-end processed semiconductor wafer is electrically connected to and aligned with a via of the front-end processed semiconductor wafer.

2. The apparatus of claim 1, wherein the via of the back-end processed semiconductor wafer comprises an annular via.

3. The apparatus of claim 1, wherein the via of the back-end processed semiconductor wafer comprises a coaxial via.

4. The apparatus of claim 3, wherein the electrically-conductive material comprises a first annular metal ring abutting an outer boundary of the coaxial via.

5. The apparatus of claim 4, wherein the electrically-conductive material further comprises a second annular metal ring abutting an inner boundary of the coaxial via, and wherein the second annular metal ring is electrically isolated from the first annular metal ring.

6. The apparatus of claim 4, wherein the coaxial via comprises a metal conductor.

7. The apparatus of claim 1, wherein the via of the back-end processed semiconductor wafer comprises a triaxial via.

8. The apparatus of claim 7, wherein the electrically-conductive material comprises a first annular metal ring abutting an outer boundary of the triaxial via.

9. The apparatus of claim 8, wherein the electrically-conductive material comprises a second annular metal ring abutting an inner boundary of the triaxial via.

10. The apparatus of claim 1, wherein the metallization layer is one of a plurality of metallization layers on the semiconductor wafer.

11. The apparatus of claim 10, wherein the via of the back-end processed semiconductor wafer extends through the plurality of metallization layers.

12. The apparatus of claim 1, wherein the metallization layer is adjacent to the substrate.

13. The apparatus of claim 1, wherein the via of the back-end processed semiconductor wafer has a longitudinal length of at least 50 μ

m.

14. The apparatus of claim 1, wherein the via of the back-end processed semiconductor wafer has a longitudinal length of at least 100 μ

m.

15. The apparatus of claim 1, further comprising an insulator, wherein the insulator bounds the electrically-conductive material.

16. The apparatus of claim 1, wherein the via of the back-end processed semiconductor wafer is one of a plurality of vias on the semiconductor wafer, and wherein the plurality of vias are spaced on a pitch not greater than 50 μ

m.

17. The apparatus of claim 1, further comprising a contact electrically coupled to the via of the back-end processed semiconductor wafer.

18. The apparatus of claim 17, wherein the contact is part of a connection comprising a rigid material that penetrates into a malleable material.

19. The apparatus of claim 17, wherein the contact is coupled to a concentric via comprising a cooling tube configured to transfer heat from an integrated circuit chip.

20. The apparatus of claim 1, wherein the via of the back-end processed semiconductor wafer has an aspect ratio between 3:

1 and 30;

1.

21. The apparatus of claim 1, wherein the via of the back-end processed semiconductor wafer has an aspect ratio between 5:

1 and 10;

1.

22. The apparatus of claim 1, wherein the back-end processed semiconductor wafer does not include electronic devices other than metal traces configured to interconnect electronic devices of the front-end processed semiconductor wafer.

23. The apparatus of claim 1, wherein the front-end processed semiconductor wafer comprises a plurality of electronic devices, and wherein the back-end processed semiconductor wafer comprises a plurality of interconnection layers configured to interconnect the plurality of electronic devices.

24. An apparatus comprising:

a back-end processed semiconductor wafer including a substrate and a plurality of metallization layers;

a via extending from an outer surface of the substrate to at least one of the metallization layers; and

an electrically-conductive material provided within the via, wherein the electrically-conductive material forms an electrically-conductive path between the outer surface of the substrate and the at least one metallization layer;

wherein the back-end processed semiconductor wafer is coupled to a front-end processed semiconductor wafer to form a hybridized electronic chip, wherein the back-end processed semiconductor wafer has not been front-end processed and the front-end processed semiconductor wafer has not been back-end processed, and wherein the via of the back-end processed semiconductor wafer is electrically connected to and aligned with a via of the front-end processed semiconductor wafer.

25. The apparatus of claim 24, wherein the via of the back-end processed semiconductor wafer comprises an annular via.

26. The apparatus of claim 24, wherein the via of the back-end processed semiconductor wafer comprises a coaxial via.

27. The apparatus of claim 26, wherein the electrically-conductive material comprises a first annular metal ring abutting an outer boundary of the coaxial via.

28. The apparatus of claim 27, wherein the electrically-conductive material further comprises a second annular metal ring abutting an inner boundary of the coaxial via, wherein the second annular metal ring is electrically isolated from the first annular metal ring.

29. The apparatus of claim 27, wherein the coaxial via comprises a metal conductor.

30. The apparatus of claim 24, wherein the via of the back-end processed semiconductor wafer comprises a triaxial via.

31. The apparatus of claim 30, wherein the electrically-conductive material comprises a first annular metal ring abutting an outer boundary of the triaxial via.

32. The apparatus of claim 31, wherein the electrically-conductive material comprises a second annular metal ring abutting an inner boundary of the triaxial via.

33. The apparatus of claim 24, wherein the via of the back-end processed semiconductor wafer extends through the plurality of metallization layers.

34. The apparatus of claim 24, wherein the at least one metallization layer is adjacent to the substrate.

35. The apparatus of claim 24, wherein the via of the back-end processed semiconductor wafer has a longitudinal length of at least 50 μ

m.

36. The apparatus of claim 24, wherein the via of the back-end processed semiconductor wafer has a longitudinal length of at least 100 μ

m.

37. The apparatus of claim 24, further comprising an insulator bounding the electrically-conductive material.

38. The apparatus of claim 24, wherein the via of the back-end processed semiconductor wafer is one of a plurality of vias on the semiconductor wafer, and wherein the plurality of vias are spaced on a pitch not greater than 50 μ

m.

39. The apparatus of claim 24, wherein the via of the back-end processed semiconductor wafer has an aspect ratio between 3:

1 and 30;

1.

40. An apparatus comprising:

a back-end processed semiconductor wafer including a substrate and a metallization layer;

a first via extending from a first outer surface of the substrate to the metallization layer;

a second via extending from the first outer surface to a second outer surface of the semiconductor wafer; and

an electrically-conductive material provided within the first via, wherein the electrically-conductive material forms an electrically-conductive path between the outer surface of the substrate and the metallization layer;

wherein the back-end processed semiconductor wafer is coupled to a front-end processed semiconductor wafer to form a hybridized electronic chip, wherein the back-end processed semiconductor wafer has not been front-end processed and the front-end processed semiconductor wafer has not been back-end processed, and wherein at least one of the first and second vias is electrically connected to and aligned with a via of the front-end processed semiconductor wafer.

41. The apparatus of claim 40, wherein the first via comprises an annular via.

42. The apparatus of claim 40, wherein the first via comprises a coaxial via.

43. The apparatus of claim 42, wherein the electrically-conductive material comprises a first annular metal ring abutting an outer boundary of the coaxial via.

44. The apparatus of claim 40, wherein the first via comprises a triaxial via.

45. The apparatus of claim 40, wherein the second via is a through-via comprising a flared end.

46. The apparatus of claim 40, wherein the second via is configured as a heat-pipe.

47. The apparatus of claim 40, wherein the second via is configured to couple with a complementary locking via of a corresponding front-end processed wafer.