Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions
First Claim
1. An integrated circuit including at least one internal operational block comprising:
- test control circuitry for initiating a test mode;
testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode, comprising;
bias current control circuitry for setting a bias current to the internal block in the test mode to emulate the more stringent operating condition; and
measurement circuitry for monitoring an operating parameter of the internal block; and
pin control circuitry for selectively outputting a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
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Accused Products
Abstract
An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
4 Citations
10 Claims
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1. An integrated circuit including at least one internal operational block comprising:
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test control circuitry for initiating a test mode; testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode, comprising; bias current control circuitry for setting a bias current to the internal block in the test mode to emulate the more stringent operating condition; and measurement circuitry for monitoring an operating parameter of the internal block; and pin control circuitry for selectively outputting a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit including at least one internal operational block comprising:
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test control circuitry for initiating a test mode; testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode, wherein the testing circuitry is operable in the test mode to test a voltage offset at a selected node of the internal block against a reduced maximum voltage offset limit value compared to a maximum voltage offset limit value in the another operating mode to assure proper operations of the internal block with a larger voltage offset at the selected node in the another operating mode; and pin control circuitry for selectively outputting a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging.
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10. An integrated circuit including at least one internal operational block comprising:
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test control circuitry for initiating a test mode; testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode, wherein the testing circuitry is operable in the test mode to vary a bias current to the internal block to emulate a worst case operating condition of the internal block in the another operating mode and in response compare an operating parameter of the internal block against a limit value; and pin control circuitry for selectively outputting a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging.
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Specification