Frequency divider circuits

• US 7,808,287 B2
• Filed: 01/15/2007
• Issued: 10/05/2010
• Est. Priority Date: 01/24/2006
• Status: Expired due to Fees

• Current Assignee: Future Waves UK Limited
• Original Assignee: Future Waves UK Limited
• Inventors: Miller, Robin James
• Primary Examiner(s): Nguyen; Hai L
• Application Number:
  US12/161,945
• Publication Number:
  US 20090251176A1
• Time in Patent Office: 1,359 Days
• Field of Search: 327/115, 327/117
• US Class Current: 327/115
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/489 A coil being added in the source circuit of a common source stage, e.g. as degeneration means
• CPC Class Codes: H03F 2200/492 A coil being added in the source circuit of a transistor amplifier stage as degenerating element
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03K 23/544 with a base which is an odd number
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A circuit for deriving an output clock signal from an input clock signal, the output clock signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number. The circuit comprises a plurality of latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of the input clock signal. An RS flip flop is coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge. Said output clock signal is provided at an output of the RS flip flop.

Claims

1. A circuit for deriving an output clock signal from an input clock signal, the output clock signal having a frequency which is 1/Nth of the frequency of the input clock signal, where N is an odd number, the circuit comprising:

a plurality of latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of the input clock signal; and

a memory element having set and reset inputs for setting and resetting an output of the element, the element being coupled to receive at one of its set and reset inputs an output from the latch ring that is switched on a rising edge of the input clock signal, and at the other of the set and reset inputs an output from the latch ring that is switched on a falling edge of the input clock signal,

said output clock signal being provided at said output of the memory element.

2. A circuit according to claim 1, wherein the number of latches in the latch ring is N+1.

3. A circuit according to claim 1, wherein said latches are D-type latches.

4. A circuit according to claim 3, wherein each said pair of latches provides a D-type flip flop.

5. A circuit according to claim 1, wherein the set input of the memory element is coupled to an output of an AND gate.

6. A circuit according to claim 5, wherein the inputs of the AND gate are coupled to respective outputs of two latches that are both triggered by the rising edge of the input clock signal, or by the falling edge.

7. A circuit according to claim 6, wherein said two latches are the second latches of successive latch pairs in the ring.

8. A circuit according to claim 1, wherein the reset input of the memory element is coupled to an output of a first latch of one of the latch pairs.

9. A circuit according to claim 1, the circuit being programmable to set the value of N from a plurality of values including odd and even values.

10. A circuit according to claim 9 wherein the set input of the memory element is coupled to an output of an AND gate, the circuit comprising a multiplexer having an input coupled to the output of said AND gate, and one or more further inputs coupled to respective outputs of latch pairs.

11. A circuit according to claim 1, the circuit comprising a multiplexer having a first input coupled to an output of said memory element, and a second input coupled to an output of one of the latch pairs.

12. A circuit according to claim 1, wherein said memory element is an edge triggered device.

13. A circuit according to claim 1, wherein said memory element is an RS flip flop.

14. A method of generating a clock signal having a frequency which is 1/Nth of the frequency of an input clock signal, where N is an odd number, using a plurality of latches configured as a latch ring, the latches being arranged in successive pairs, each pair of latches comprising a first latch that switches on one of the rising or falling edge of the input clock signal, and a second latch that switches on the other of the rising or falling edge of the input clock signal, the method comprising:

setting the output of a memory using an output from the latch ring that is switched on one of a rising or falling edge of the input clock signal, and resetting the output of the memory element on the other of the rising or falling edge of the input clock signal,

said output clock signal being provided at an output of the memory element.