PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications

• US 7,808,504 B2
• Filed: 10/26/2007
• Issued: 10/05/2010
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucid Information Technology, Ltd.
• Inventors: Bakalash, Reuven, Remez, Offir, Fogel, Efi
• Primary Examiner(s): Nguyen, Hau H
• Application Number:
  US11/978,228
• Publication Number:
  US 20080129745A1
• Time in Patent Office: 1,075 Days
• Field of Search: 345/505, 345/519, 345/506, 345/419, 345/520, 345502-504
• US Class Current: 345/519
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUs) supplied from the same or different vendors. The graphics subsystem include a graphics controller hub (GCH) chip located on a CPU bus, and having Multi-Pipeline Core Logic (MP-CL) circuitry including a routing unit and a control unit. The plurality of different GPUs are interfaced with the GCH chip. Each different GPU supports a GPU-driven pipeline core having a frame buffer (FB) for storing a fragment of pixel data. The GPU-driven pipeline cores are arranged in a parallel architecture and operated according to a parallelization mode of operation, so that said GPU-driven pipeline cores process data in a parallel manner. In one illustrative embodiment, the different GPUs are located (i) within an integrated graphics device (IGD) within the GCH chip, and also (ii) on one or more external GPU-based graphics cards from the same or different vendors. In another illustrative embodiment, the different GPUs are located on a plurality of external GPU-based graphics cards from different vendors. Diverse illustrative embodiments are disclosed.

Claims

1. A PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUs) from same or different vendors, in a manner transparent to graphics applications, said PC-based computing system comprising:

system memory for storing software graphics applications, software drivers and graphics libraries;

an operating system (OS), stored in said system memory;

one or more graphics applications, stored in said system memory, for generating a stream of graphics commands and geometrical data supporting the representation of one or more 3D objects in a scene having 3D geometrical characteristics and the viewing of images of said one or more 3D objects in said scene during an interactive process carried out between said PC-based computing system and a user thereof;

one or more graphics libraries, stored in said system memory, for storing data used to implement said stream of graphics commands and geometrical data;

a central processing unit (CPU) on a motherboard for executing said OS, said graphics applications, and said graphics libraries;

a CPU bus;

a display surface for displaying said images by graphically displaying frames of pixel data;

a graphics subsystem integrated within said PC-based computing system and supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUs) supplied from the same or different vendor, and in a manner transparent to said one or more graphics applications, and wherein said graphics subsystem includes a graphics controller hub (GCH) chip located on said CPU bus, and having Multi-Pipeline Core Logic (MP-CL) circuitry including a routing unit and a control unit;

wherein said plurality of different GPUs are interfaced with said GCH chip,

wherein each said different GPU supports a GPU-driven pipeline core having a frame buffer (FB) for storing a fragment of pixel data, and

wherein said GPU-driven pipeline cores are arranged in a parallel architecture and operated according to a parallelization mode of operation, so that said GPU-driven pipeline cores process data in a parallel manner, and

wherein at least one of said GPU-driven pipeline cores includes a display interface interfacing with said display surface;

a plurality of vendor-supplied software GPU drivers, stored in said system memory, for said plurality of different GPUs;

wherein each said vendor-supplied GPU driver (i) allows the GPU-driven pipeline core and said GPU to interact with said OS and said graphic libraries, and (ii) controls said GPU during the running of said graphics application; and

a plurality of software multi-pipe drivers, stored in said system memory, and including (i) a first software module for profiling and analyzing said graphics application, including analyzing incoming commands, and collecting and analyzing parameters including performance data selected from the group consisting of memory speed, memory usage in bytes, total pixels rendered, geometric data entering rendering, frame rate, workload of each GPU-driven pipeline core, load balance among said GPU-driven pipeline cores, volumes of transferred data, textures count, and depth complexity, and (ii) a second software module for controlling said parallelization mode of operation;

wherein said control unit accepts commands from said software multi-pipe drivers, over said CPU bus, and controls components within said GCH chip, including said routing unit;

wherein said routing unit feeds back performance data to said software multi-pipe drivers, for balancing the data load among said GPU-driven pipeline cores during said parallelization mode of operation;

wherein, for each image of said 3D object to be generated and displayed on said display surface, the following operations are performed;

(i) said routing unit routes said stream of graphic commands and geometrical data, or a portion thereof, from said CPU to one or more of said GPU-driven pipeline cores,

(ii) one or more of said GPU-driven pipeline cores process said stream of graphic commands and geometrical data, or a portion thereof, during the generation of each said frame, while operating in said parallelization mode, so as to generate pixel data corresponding to at least a portion of said image, and

(iii) said routing unit routes pixel data output from one or more of said GPU-driven pipeline cores during the composition of each frame of pixel data, corresponding to a final image, for display on said display surface.

2. The PC-based computing system of claim 1, wherein said GCH chip further comprises a memory unit for storing intermediate processing results from one or more of said GPU-driven pipeline cores, and data required for composition and transferring frames of pixel data for display.

3. The PC-based computing system of claim 1, wherein said geometrical data comprises a set of scene polygons, textures and vertex objects.

4. The PC-based computing system of claim 1, wherein said graphics commands includes commands selected from the group consisting of display lists and display vertex arrays.

5. The PC-based computing system of claim 1, wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.

6. The PC-based computing system of claim 1, wherein when said parallelization mode of operation is a time division mode, the GPU in each said GPU-driven pipeline core renders a different frame of pixel data for display on said display surface at a different moment of time.

7. The PC-based computing system of claim 1, wherein when said parallelization mode of operation is an image division mode, each GPU on each said external GPU-driven pipeline core renders a subset of the pixels used to compose each frame of pixel data to be displayed on said display surface.

8. The PC-based computing system of claim 1, wherein when said parallelization mode of operation is an object division mode, the 3D object which is to be displayed as an image consisting of a frame of pixels, is decomposed into said stream of graphic commands and geometrical data which are distributed to said GPU-driven pipeline core for rendering the frames of pixel data compositing the images to be displayed on said display surface.

9. The PC-based computing system of claim 8, wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygons.

10. The PC-based computing system of claim 1, wherein said software multi-pipe drivers further comprise a third software module installed in said system memory for continuously analyzing substantially all incoming commands, including state commands, transferring certain state commands and some of the data all of said GPU-driven pipeline cores so as to preserve the valid state across said GPU-driven pipeline cores.

11. The PC-based computing system of claim 10, wherein said third software modules uses inputs from (i) the registers of said GPU-driven pipeline cores, and (ii) registers of said control unit, and graphic API commands.

12. The PC-based computing system of claim 1, wherein said second software module controls said parallelization mode of operation during the generation of each said frame of pixel data during the running of said graphics application.

13. The PC-based computing system of claim 1, wherein said GPU-driven pipeline cores are arranged in a parallel architecture and operated according to one or more parallelization modes of operation, determined during the generation of each said frame of pixel data, so that said GPU-driven pipeline cores process data in a parallel manner.

14. The PC-based computing system of claim 13, wherein said second software module dynamically determins and controls said parallelization mode of operation during any particular frame of pixel data generation and display.

15. The PC-based computing system of claim 14, wherein said second software module dynamically determines and controls said parallelization mode of operation during any particular frame of pixel data generation and display, based on factors including the time required to render previous frames of pixel data and bottlenecks exhibited in vertex processing and pixel processing during the rendering of said previous frames of pixel data.

16. The PC-based computing system of claim 13, wherein said parallelization mode of operation is selected from the group consisting of an object division mode, an image division mode and a time division mode, and wherein said second software module dynamically determines and controls said parallelization mode during any particular frame of pixel data generation and display, based on any combination of said object division mode, said image division mode and said time division mode.

17. The PC-based computing system of claim 1, wherein said GCH chip is a memory bridge chip, which interfaces with said system memory.

18. The PC-based computing system of claim 1, wherein said GCH chip is realized as a system-on-a-chip (SOC) architecture.

19. The PC-based computing system of claim 1, wherein said different GPUs are located (i) within an integrated graphics device (IGD) within said GCH chip, and also (ii) on one or more external GPU-based graphics cards from the same or different vendors.

20. The PC-based computing system of claim 1, wherein said different GPUs are located on a plurality of external GPU-based graphics cards from different vendors.

21. The PC-based computing system of claim 1, wherein said CGH chip further comprises a compositing unit for compositing each frame of pixel data, corresponding to said final image, for display on said display surface.

22. The PC-based computing system of claim 21, wherein said routing unit routes pixel data output from one or more of said GPU-driven pipeline cores to said compositing unit, during the composition of each frame of pixel data, corresponding to said final image, for display on said display surface.