Scalable high performance 3D graphics
First Claim
1. A node for use in a 3D graphics hardware accelerator implemented as a plurality of nodes connected to a ring, the node comprising:
- a loop interface for receiving packets from a neighboring node on the ring and for transmitting packets to another neighboring node on the ring;
a memory port to a local memory sub-system;
a render stage coupled to the loop interface and to the memory port, the local memory sub-system storing a texture store dedicated to the render stage, the render stage for receiving graphics primitive loop packets via the loop interface, executing the graphics rendering specified in the graphics primitive loop packets including accessing via the memory port the texture store in the local memory sub-system as required by the graphics primitive loop packet, and generating corresponding draw pixel loop packets;
a sample fill stage coupled to the loop interface and to the memory port, the local memory sub-system storing an interleave of a super-sampled frame buffer dedicated to the sample fill stage, the sample fill stage for receiving draw pixel loop packets via the loop interface and, as specified by the draw pixel loop packets, performing via the memory port a conditional sample update function of samples and/or pixels in the interleave of the super-sampled frame buffer stored in the local memory sub-system; and
a video output stage coupled to the loop interface and to the memory port, the interleave of the super-sampled frame buffer further dedicated to the video output stage, the video output stage for receiving video pixel loop packets via the loop interface and, as specified by the video pixel loop packets, retrieving via the memory port samples and/or pixels in the interleave stored in the local memory sub-system to modify the video pixel loop packets, and transmitting the modified video pixel loop packets via the loop interface.
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Accused Products
Abstract
A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
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Citations
31 Claims
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1. A node for use in a 3D graphics hardware accelerator implemented as a plurality of nodes connected to a ring, the node comprising:
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a loop interface for receiving packets from a neighboring node on the ring and for transmitting packets to another neighboring node on the ring; a memory port to a local memory sub-system; a render stage coupled to the loop interface and to the memory port, the local memory sub-system storing a texture store dedicated to the render stage, the render stage for receiving graphics primitive loop packets via the loop interface, executing the graphics rendering specified in the graphics primitive loop packets including accessing via the memory port the texture store in the local memory sub-system as required by the graphics primitive loop packet, and generating corresponding draw pixel loop packets; a sample fill stage coupled to the loop interface and to the memory port, the local memory sub-system storing an interleave of a super-sampled frame buffer dedicated to the sample fill stage, the sample fill stage for receiving draw pixel loop packets via the loop interface and, as specified by the draw pixel loop packets, performing via the memory port a conditional sample update function of samples and/or pixels in the interleave of the super-sampled frame buffer stored in the local memory sub-system; and a video output stage coupled to the loop interface and to the memory port, the interleave of the super-sampled frame buffer further dedicated to the video output stage, the video output stage for receiving video pixel loop packets via the loop interface and, as specified by the video pixel loop packets, retrieving via the memory port samples and/or pixels in the interleave stored in the local memory sub-system to modify the video pixel loop packets, and transmitting the modified video pixel loop packets via the loop interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification