Transient storage device emulation using resistivity-sensitive memory

• US 7,808,809 B2
• Filed: 12/03/2008
• Issued: 10/05/2010
• Est. Priority Date: 10/17/2007
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Norman, Robert
• Primary Examiner(s): DINH, SON T
• Application Number:
  US12/315,445
• Publication Number:
  US 20090106014A1
• Time in Patent Office: 671 Days
• Field of Search: 365/63, 365/163, 365/185.18, 365/185.29
• US Class Current: 365/63
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another.

Claims

1. A transient storage device, comprising:

a FLASH emulation interface circuitry positioned in a logic plane and operative to electrically communicate with a plurality of signals configured for data operations to FLASH memory, the plurality of signals including an address signal and at least one data operation signal; and

a non-volatile memory array in contact with the logic plane and fabricated over the FLASH emulation interface circuitry, the non-volatile memory array is electrically coupled with the FLASH emulation interface circuitry, the non-volatile memory array including a plurality of memory cells,

each memory cell including a first terminal and a second terminal and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the first and second terminals, the data is retained in the absence of power, data is written by applying a write voltage across the first and second terminals, a magnitude of the write voltage is less than the a magnitude of the read voltage,

wherein the FLASH emulation interface circuitry is operative to perform data operations on the non-volatile memory array in response to the plurality of signals and the data operations emulate FLASH memory data operations, and

wherein the FLASH emulation interface circuitry performs a write operation to the non-volatile memory array without having to perform an erase operation prior to the write operation.

2. The transient storage device of claim 1, wherein the logic plane is fabricated in a substrate.

3. The transient storage device of claim 1, wherein the non-volatile memory array comprises a two-terminal cross-point memory array.

4. A transient storage device, comprising:

a FLASH emulation interface circuitry positioned in a logic plane and operative to electrically communicate with a plurality of signals configured for data operations to FLASH memory, the plurality of signals including an address signal and at least one data operation signal; and

a non-volatile memory array in contact with the logic plane and fabricated over the FLASH emulation interface circuitry, the non-volatile memory array is electrically coupled with the FLASH emulation interface circuitry, the non-volatile memory array including a plurality of memory cells, each memory cell including a first terminal and a second terminal and operative to store data as plurality of conductivity profiles that can be determined by applying a read voltage across the first and second terminals, the data is retained in the absence of power, data is written by applying a write voltage across the first and second terminals, a magnitude of the write voltage is less than the a magnitude of the read voltage,

wherein the FLASH emulation interface circuitry is to perform data operations on the non-volatile memory array in response to the plurality of signals and the data operations emulate FLASH memory data operation,

wherein the FLASH emulation interface circuitry performs a write operation to the non-volatile memory array without having to perform an erase operation prior to the write operation,

wherein each memory cell further comprises a two-terminal memory element electrically in series with its first and second terminals, the two-terminal memory element including a mixed ionic electronic conductor including mobile ions, and an electrolytic tunnel barrier in contact with and electrically in series with the mixed ionic electronic conductor, and

wherein application of the write voltage is operative to transport the mobile ions and cause a change in a conductivity of the two-terminal memory element, and the change in the conductivity is indicative of stored data written to the two-terminal memory element by the application of the write voltage.

5. The transient storage device of claim 4, wherein the write voltage comprises a programming voltage applied across the first and second terminals and operative to transport the mobile ions from the mixed valence conductive oxide to the electrolytic tunnel barrier and the change in the conductivity is indicative of data stored as a programmed state.

6. The transient storage device of claim 4, wherein the write voltage comprises an erase voltage applied across the first and second terminals and operative to transport the mobile ions from the electrolytic tunnel barrier to the mixed valence conductive oxide and the change in the conductivity is indicative of data stored as an erased state.

7. A transient storage device, comprising:

a FLASH emulation interface circuitry positioned in a logic plane and, operative to electrically communicate with a plurality of signals configured for data operations to FLASH memory, the plurality of signals including an address signal and at least one data operation signal;

a non-volatile memory array in contact with the logic plane and fabricated over the FLASH emulation interface circuitry the non-volatile memory array is electrically coupled with the FLASH emulation interface circuitry, the non-volatile memory array including a plurality of memory cells,

each memo cell including a first terminal and a second terminal and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the first and second terminals, the data is retained in the absence of power, data is written by applying a write voltage across the first and second terminals, a magnitude of the write voltage is less than the a magnitude of the read voltage,

wherein the FLASH emulation interface circuitry is operative to perform data operations on the non-volatile memory array in response to the plurality of signals and the data operations emulate FLASH memory data operations, and

wherein the FLASH emulation interface circuitry performs a write operation to the non-volatile memory array without having to perform an erase operation prior to the write operation; and

a transportable housing configured to house the logic plane, the FLASH emulation interface circuitry, and the non-volatile memory array, the transportable housing including

an electrical interface configured to electrically couple the FLASH emulation interface circuitry with a plurality of signals from a host system that performs the data operations, and

a mechanical interface configured to mechanically couple the transportable housing with a signal node of the host system and to mechanically couple the electrical interface with the plurality of signals from the host system.

8. The transient storage device of claim 7, wherein the transportable housing is configured to be carried by a user, the user operative to connect the mechanical interface with the signal node of the host system to electrically couple the electrical interface with the plurality of signals from the host system and operative to disconnect the mechanical interface from the signal node of the host system to electrically decouple the electrical interface with the plurality of signals from the host system.

9. The transient storage device of claim 7, wherein the signal node comprises a USB port.

10. The transient storage device of claim 7, wherein the signal node comprises a SD card port.

11. The transient storage device of claim 7, wherein the signal node comprises a FLASH memory card port.

12. A transient storage device comprising:

a FLASH emulation interface circuitry positioned in a logic plane and operative to electrically communicate with a plurality of signals configured for data operations to FLASH memory, the plurality of signals including an address signal and at least one data operation signal; and

a plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is vertically stacked upon another of the plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is in contact with the logic plane, and the plurality of the non-volatile memory arrays are fabricated over and electrically coupled with the FLASH emulation interface circuitry, each non-volatile memory array including a plurality of memory cells,

each memory cell including a first terminal and a second terminal and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the first and second terminals, the data is retained in the absence of power, data is written by applying a write voltage across the first and second terminals, a magnitude of the write voltage is less than the a magnitude of the read voltage,

wherein the FLASH emulation interface circuitry is operative to perform data operations on at least one of the plurality of non-volatile memory arrays in response to the plurality of signals and the data operations emulate FLASH memory data operations, and

wherein the FLASH emulation interface circuitry performs a write operation to at least one of the plurality of non-volatile memory arrays without having to perform an erase operation prior to the write operation.

13. The transient storage device of claim 12, wherein the plurality of non-volatile memory arrays comprises two-terminal cross-point memory arrays.

14. A transient storage device comprising:

a FLASH emulation interface circuitry positioned in a logic plane and operative to electrically communicate with a plurality of signals configured for data operations to FLASH memory, the plurality of signals including an address signal and at least one data operation signal;

a plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is vertically stacked upon another of the plurality, of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is in contact with the logic plane, and the plurality the non-volatile memory arrays are fabricated over and electrically coupled with the FLASH emulation interface circuitry, each non-volatile memory array including a plurality of memory cells,

each memo cell including a first terminal and a second terminal and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the first and second terminals, the data is retained in the absence of power, data is written by applying a write voltage across the first and second terminals a magnitude of the write voltage is less than the a magnitude of the read voltage,

wherein the FLASH emulation interface circuitry is operative to perform data operations on at least one of the plurality of non-volatile memory arrays in response to the plurality of signals and the data operations emulate FLASH memory data operations,

wherein the FLASH emulation interface circuitry performs a write operation to at least one of the plurality of non-volatile arrays without having to perform an erase operation prior to the write operation; and

a transportable housing configured to house the logic plane, the FLASH emulation interface circuitry, and the plurality of non-volatile memory arrays, the transportable housing including

an electrical interface configured to electrically couple the FLASH emulation interface circuitry with a plurality of signals from a host system that performs the data operations, and

a mechanical interface configured to mechanically couple the transportable housing with a signal node of the host system and to mechanically couple the electrical interface with the plurality of signals.

15. The transient storage device of claim 14, wherein the transportable housing is configured to be carried by a user, the user operative to connect the mechanical interface with the signal node of the host system to electrically couple the electrical interface with the plurality of signals from the host system and operative to disconnect the mechanical interface from the signal node of the host system to electrically decouple the electrical interface with the plurality of signals from the host system.

16. The transient storage device of claim 14, wherein the signal node comprises a USB port.

17. The transient storage device of claim 14, wherein the signal node comprises a SD card port.

18. The transient storage device of claim 14, wherein the signal node comprises a FLASH memory card port.

19. A transient storage device comprising:

a FLASH emulation interface circuitry positioned in a logic plane and operative to electrically communicate with a plurality of signals configured for data operations to FLASH memory, the plurality of signals including an address signal and at least one data operation signal; and

a plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is vertically stacked upon another of the plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is in contact with the logic plane, and the plurality of the non-volatile memory arrays are fabricated over and electrically coupled with the FLASH emulation interface circuitry, each non-volatile memory array Including a plurality of memory cells,

each memory cell including a first terminal and a second terminal and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the first and second terminals, the data is retained in the absence of power, data is written by applying a write voltage across the first and second terminals, a magnitude of the write voltage is less than the a magnitude of the read voltage,

wherein the FLASH emulation Interface circuitry is operative to perform data operations on at least one of the plurality of non-volatile memory arrays in response to the plurality of signals and the data operations emulate FLASH memory data operations,

wherein the FLASH emulation interface circuitry performs a write operation to at least one of the plurality of non-volatile memory arrays without having to perform an erase operation priror to the write operations,

wherein each memory cell further comprises a two-terminal memory element electrically in series with its first and second terminals, the two-terminal memory element including

a mixed ionic electronic conductor including mobile ions, and

an electrolytic tunnel barrier in contact with and electrically in series with the mixed ionic electronic conductor, and

wherein application of the write voltage is operative to transport the mobile ions and cause a change in a conductivity of the two-terminal memory element, and the change in the conductivity is indicative of stored data written to the two-terminal memory element by the application of the write voltage.

20. The transient storage device of claim 19, wherein the write voltage comprises a programming voltage applied across the first and second terminals and operative to transport the mobile ions from the mixed valence conductive oxide to the electrolytic tunnel barrier and the change in the conductivity is indicative of data stored as a programmed state.

21. The transient storage device of claim 19, wherein the write voltage comprises an erase voltage applied across the first and second terminals and operative to transport the mobile ions from the electrolytic tunnel barrier to the mixed valence conductive oxide and the change in the conductivity is indicative of data stored as an erased state.

22. A transient storage device comprising:

a FLASH emulation interface circuitry positioned in a logic plane and operative to electrically communicate with a plurality of signals configured for data operations to FLASH memory, the plurality of signals including an address signal and at least one data operation signal;

a plurality of the non-volatile memory arrays, at least one of the plurality of the non-volatile memory arrays is vertically stacked upon another of the plurality of the non-volatile memory array at least one of the plurality of the non-volatile memory arrays is in contact with the logic plane, and the plurality of the non-volatile memory arrays are fabricated over and electrically coupled with the FLASH emulation interface circuitry, each non-volatile memory array including a plurality of memory cells,

each memory cell including a first terminal and a second terminal and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the first and second terminals, the data is retained in the absence of power, data is written by applying a write voltage across the first and second terminals, a magnitude of the write voltage is less than the a magnitude of the read voltage,

wherein the FLASH emulation Interface circuitry is operative to perform data operations on at least one of the plurality of non-volatile memory arrays in response to the plurality of signals and the data operations emulate FLASH memory data operations,

wherein the FLASH emulation interface circuitry performs a write operation to at least one of the plurality of non-volatile memory arrays without having to perform an erase operation prior to the write operation; and

an emulation interface circuitry positioned in the logic plane and operative to electrically communicate with a plurality of signals configured for data operations to a non-FLASH memory type, the plurality of signals including an address signal and at least one data operation signal, and

wherein the emulation interface circuitry is operative to perform data operations on at least one of the plurality of non-volatile memory arrays in response to the plurality of signals and the data operations emulate memory data operations to the non-FLASH memory type.

23. The transient storage device of claim 22, wherein the non-FLASH memory type comprises a SRAM.

24. The transient storage device of claim 22, wherein the non-FLASH memory type comprises a DRAM.

25. The transient storage device of claim 22, wherein the non-FLASH memory type comprises a ROM.