Secondary injection for NROM

• US 7,808,818 B2
• Filed: 12/28/2006
• Issued: 10/05/2010
• Est. Priority Date: 01/12/2006
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/646,395
• Publication Number:
  US 20070159880A1
• Time in Patent Office: 1,377 Days
• Field of Search: 365/185.03, 365/185.24, 365/185.27
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

Secondary electron injection (SEI) is used for programming NVM cells having separate charge storage areas in an ONO layer, such as NROM cells. Various combinations of low wordline voltage (Vwl), negative substrate voltabe (Vb), and shallow and deep implants facilitate the process. Second bit problems may be controlled, and retention and punchthrough may be improved. Lower SEI programming current may result in relaxed constraints on bitine resistance, number of contacts required, and power supply requirements.

Claims

1. A method of injecting electrons into charge storage areas of a non-volatile memory (NVM) cell comprising an ONO layer, the method comprising:

utilizing secondary electron injection (SEI) to perform a given electron injection operation, and

wherein a threshold voltage (Vt) for the cell is defined, and further comprising;

applying a gate voltage (Vg) of approximately Vt+3 V during the operation.

2. The method of claim 1, wherein:

the NVM cell is a nitride read only memory (NROM) cell.

3. The method of claim 1, wherein:

the given electron injection operation is programming at least one charge storage area of the cell.

4. The method of claim 1, further comprising:

enhancing secondary electron injection (SEI) while substantially reducing channel hot electron (CHE) injection during the given electron injection operation.

5. The method of claim 1, wherein:

SEI accounts for at least 65% of the electrons injected into a selected one of the charge storage areas of the cell during the given electron injection operation.

6. The method of claim 1, further comprising:

applying a gate voltage (Vg) which is sufficiently low that CHE is substantially eliminated.

7. The method of claim 1, wherein:

Vt is approximately +1.8 volts.

8. The method of claim 1, further comprising:

applying a source voltage (Vs) of approximately 0;

applying a drain voltage of approximately 3.0-4.5 volts; and

applying a substrate voltage (Vb) of approximately 0 to −

2 volts.

9. The method of claim 1, further comprising:

applying a substrate voltage (Vb) of approximately 0 to −

2 volts.

10. A method of injecting electrons into charge storage areas of a non-volatile memory (NVM) cell comprising an ONO layer, the method comprising:

utilizing secondary electron injection (SEI) to perform a given electron injection operation, and further comprising;

injecting the electrons into charge storage areas which are above two bitline diffusions defining the cell; and

constructing the cell so that a read mechanism is insensitive to electrons injected far from the diffusion.

11. The method of claim 10, wherein the charge storage areas are located above bitline diffusions defining the cell, and further comprising:

implanting shallow pocket implants (PI-1) in the channel, adjacent the diffusions.

12. The method of claim 11, wherein:

the shallow pocket implants comprise boron (or indium, or combinations thereof).

13. The method of claim 11, further comprising:

implanting the shallow pocket implants at a dosage of approximately 1.5.times.10.sup.13 per cm.sup.2 at 60 KeV and at an angle of 25-degrees to the right and left of vertical.

14. A method of injecting electrons into charge storage areas of a non-volatile memory (NVM) cell comprising an ONO layer, the method comprising:

utilizing secondary electron injection (SEI) to perform a given electron injection operation, and further comprising;

implanting a first threshold voltage implant (#1) shallow in the channel.

15. The method of claim 14, wherein:

the first threshold voltage implant (#1) extends from substantially the surface of the substrate to a first depth (d1) below the surface of the substrate.

16. The method of claim 14, wherein:

the first depth is approximately ¼

-⅓

of a junction depth below the surface of the substrate.

17. The method of claim 16, wherein:

the junction depth is 80-100 nm.

18. The method of claim 14, wherein:

the first threshold voltage implant (#1) has a low boron concentration, such as 5-10.times.10.sup.2/cm.sup.2 boron.

19. A method of injecting electrons into charge storage areas of a non-volatile memory (NVM) cell comprising an ONO layer, the method comprising:

utilizing secondary electron injection (SEI) to perform a given electron injection operation, and

wherein the NVM cell is disposed in a substrate, and further comprising;

providing means for enhancing generation of secondary electrons (e3) deep in the substrate.

20. The method of claim 19, wherein:

the means for enhancing generation of secondary electrons (e3) comprises a deep pocket implant (PI-2) formed deep within the substrate.

21. The method of claim 20, wherein:

the deep pocket implant comprises boron.

22. The method of claim 20, wherein:

the deep pocket implant is formed with a dose of 0.5-6.times.10.sup.13/cm.sup.2 at an angle of 0-15.degree. and energy of 10-20 Kev.

23. The method of claim 20, wherein:

the deep pocket implant is located approximately beneath a corresponding shallow pocket implant, spaced apart from both the shallow pocket implant and the diffusion.

24. The method of claim 20, wherein:

the deep pocket implant extends from approximately half a depth of the bitline diffusion to at least the depth of the bitline diffusion.

25. The method of claim 19, wherein:

the means for enhancing generation of secondary electrons (e3) comprises a Vt implant (Vt #3) formed deep within the substrate.

26. The method of claim 25, wherein:

the Vt implant (Vt #3) comprises boron.

27. The method of claim 25, wherein:

the Vt implant (Vt #3) is formed with a dose of 1-5.times.10.sup.13/cm.sup.2.

28. The method of claim 25, wherein:

the charge storage areas are located above two bitline diffusions defining the cell; and

the Vt implant (Vt #3) is located approximately beneath a shallow pocket implant, spaced apart from both the shallow pocket implant and the diffusions.

29. The method of claim 25, wherein:

the charge storage areas are located above two bitline diffusions defining the cell;

and the Vt implant (Vt #3) extends from approximately half a depth of the bitline diffusion to at least the depth of the bitline diffusion.

30. A method of injecting electrons into charge storage areas of a non-volatile memory (NVM) cell comprising an ONO layer, the method comprising:

utilizing secondary electron injection (SEI) to perform a given electron injection operation, and wherein;

the NROM cell is formed in a cell well having a background concentration of approximately 1.0-1.5.times.10.sup.17/cm.sup.3 boron (or indium).

31. The method of claim 30, wherein:

the NROM cell is formed in a cell well having a background concentration of approximately 1.0.times.10.sup.17/cm.sup.3 boron.